mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
53dfa78e41
commit
81092dc20a
@ -7,7 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in
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// This file contains the entry points for global functions defined in
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// the LLVM Mips back-end.
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//
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//===----------------------------------------------------------------------===//
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@ -59,7 +59,7 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips2 ISA Support">;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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"Mips32 ISA Support",
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[FeatureCondMov, FeatureBitCount]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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@ -30,7 +30,7 @@
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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@ -53,14 +53,14 @@ namespace {
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return "Mips Assembly Printer";
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier = 0);
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void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier = 0);
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void printSavedRegsBitmask(raw_ostream &O);
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void printHex32(unsigned int Value, raw_ostream &O);
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@ -94,12 +94,12 @@ namespace {
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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@ -110,9 +110,9 @@ namespace {
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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@ -122,7 +122,7 @@ namespace {
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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@ -168,7 +168,7 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
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O << "0x";
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for (int i = 7; i >= 0; i--)
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for (int i = 7; i >= 0; i--)
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O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
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}
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@ -191,9 +191,9 @@ void MipsAsmPrinter::emitFrameDirective() {
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}
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/// Emit Set directives.
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const char *MipsAsmPrinter::getCurrentABIString() const {
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const char *MipsAsmPrinter::getCurrentABIString() const {
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switch (Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O64: return "abiO64";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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@ -203,7 +203,7 @@ const char *MipsAsmPrinter::getCurrentABIString() const {
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llvm_unreachable("Unknown Mips ABI");
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return NULL;
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}
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}
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
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@ -214,7 +214,7 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() {
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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emitFrameDirective();
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printSavedRegsBitmask(OS);
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@ -226,7 +226,7 @@ void MipsAsmPrinter::EmitFunctionBodyStart() {
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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// break with BB logic.
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
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OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
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@ -236,7 +236,7 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
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/// isBlockOnlyReachableByFallthough - Return true if the basic block has
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/// exactly one predecessor and the control transfer mechanism between
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/// the predecessor and this block is a fall-through.
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
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const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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@ -246,16 +246,16 @@ bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *
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if (const BasicBlock *bb = Pred->getBasicBlock())
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if (isa<SwitchInst>(bb->getTerminator()))
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return false;
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return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0])
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo, O);
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@ -287,7 +287,7 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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if (MI->getOpcode() == Mips::LUi)
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O << "%hi(";
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else
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O << "%lo(";
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O << "%lo(";
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break;
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}
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@ -323,7 +323,7 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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if (MO.getOffset())
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O << "+" << MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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@ -336,7 +336,7 @@ void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
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const MachineOperand &MO = MI->getOperand(opNum);
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if (MO.isImm())
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O << (unsigned short int)MO.getImm();
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else
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else
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printOperand(MI, opNum, O);
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}
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@ -352,8 +352,8 @@ printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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return;
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}
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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printOperand(MI, opNum, O);
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O << "(";
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@ -365,12 +365,12 @@ void MipsAsmPrinter::
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printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier) {
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const MachineOperand& MO = MI->getOperand(opNum);
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O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
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O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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// FIXME: Use SwitchSection.
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// Tell the assembler which ABI we are using
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OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
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@ -383,11 +383,11 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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}
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// return to previous section
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OutStreamer.EmitRawText(StringRef("\t.previous"));
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OutStreamer.EmitRawText(StringRef("\t.previous"));
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}
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// Force static initialization.
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extern "C" void LLVMInitializeMipsAsmPrinter() {
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extern "C" void LLVMInitializeMipsAsmPrinter() {
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RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
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RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
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}
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@ -1,23 +1,23 @@
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//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for Mips architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>:
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class CCIfSubtarget<string F, CCAction A>:
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CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Mips O32 Calling Convention
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//===----------------------------------------------------------------------===//
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// Only the return rules are defined here for O32. The rules for argument
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// Only the return rules are defined here for O32. The rules for argument
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// passing are defined in MipsISelLowering.cpp.
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def RetCC_MipsO32 : CallingConv<[
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// i32 are returned in registers V0, V1
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@ -41,15 +41,15 @@ def CC_MipsEABI : CallingConv<[
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
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// Single fp arguments are passed in pairs within 32-bit mode
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CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
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// Single fp arguments are passed in pairs within 32-bit mode
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CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
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CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
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CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
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CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[F12, F14, F16, F18]>>>,
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// The first 4 doubl fp arguments are passed in single fp registers.
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[D6, D7, D8, D9]>>>,
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// Integer values get stored in stack slots that are 4 bytes in
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@ -52,19 +52,19 @@ class MipsDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const MipsSubtarget &Subtarget;
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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}
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private:
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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@ -116,11 +116,11 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
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(Addr.getOpcode() == ISD::TargetConstantPool) ||
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if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
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(Addr.getOpcode() == ISD::TargetConstantPool) ||
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(Addr.getOpcode() == ISD::TargetJumpTable)){
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr;
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@ -130,8 +130,8 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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@ -158,10 +158,10 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
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if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
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Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
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Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
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SDValue LoVal = Addr.getOperand(1);
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SDValue LoVal = Addr.getOperand(1);
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if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
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Base = Addr.getOperand(0);
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Offset = LoVal.getOperand(0);
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@ -176,7 +176,7 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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}
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SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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MVT::SimpleValueType NVT =
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MVT::SimpleValueType NVT =
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N->getValueType(0).getSimpleVT().SimpleTy;
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if (!Subtarget.isMips1() || NVT != MVT::f64)
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@ -199,14 +199,14 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
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DebugLoc dl = N->getDebugLoc();
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// The second load should start after for 4 bytes.
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// The second load should start after for 4 bytes.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
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MVT::i32,
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CP->getAlignment(),
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CP->getOffset()+4,
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Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
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MVT::i32,
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CP->getAlignment(),
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CP->getOffset()+4,
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CP->getTargetFlags());
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else
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return NULL;
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@ -220,16 +220,16 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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// Generate:
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// lwc $f0, X($3)
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// lwc $f1, X+4($3)
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SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset0, Base, Chain);
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, NVT), 0);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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MVT::f64, Undef, SDValue(LD0, 0));
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SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset1, Base, SDValue(LD0, 1));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
|
||||
MVT::f64, I0, SDValue(LD1, 0));
|
||||
|
||||
ReplaceUses(SDValue(N, 0), I1);
|
||||
@ -241,7 +241,7 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
|
||||
|
||||
SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
|
||||
|
||||
if (!Subtarget.isMips1() ||
|
||||
if (!Subtarget.isMips1() ||
|
||||
N->getOperand(1).getValueType() != MVT::f64)
|
||||
return NULL;
|
||||
|
||||
@ -265,12 +265,12 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
|
||||
DebugLoc dl = N->getDebugLoc();
|
||||
|
||||
// Get the even and odd part from the f64 register
|
||||
SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
|
||||
SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
|
||||
dl, MVT::f32, N1);
|
||||
SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
|
||||
dl, MVT::f32, N1);
|
||||
|
||||
// The second store should start after for 4 bytes.
|
||||
// The second store should start after for 4 bytes.
|
||||
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
|
||||
Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
|
||||
else
|
||||
@ -315,26 +315,26 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
}
|
||||
|
||||
///
|
||||
// Instruction Selection not handled by the auto-generated
|
||||
// Instruction Selection not handled by the auto-generated
|
||||
// tablegen selection should be handled here.
|
||||
///
|
||||
///
|
||||
switch(Opcode) {
|
||||
|
||||
default: break;
|
||||
|
||||
case ISD::SUBE:
|
||||
case ISD::SUBE:
|
||||
case ISD::ADDE: {
|
||||
SDValue InFlag = Node->getOperand(2), CmpLHS;
|
||||
unsigned Opc = InFlag.getOpcode(); (void)Opc;
|
||||
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
||||
(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
||||
assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
||||
(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
||||
"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
|
||||
|
||||
unsigned MOp;
|
||||
if (Opcode == ISD::ADDE) {
|
||||
CmpLHS = InFlag.getValue(0);
|
||||
MOp = Mips::ADDu;
|
||||
} else {
|
||||
} else {
|
||||
CmpLHS = InFlag.getOperand(0);
|
||||
MOp = Mips::SUBu;
|
||||
}
|
||||
@ -346,7 +346,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
|
||||
EVT VT = LHS.getValueType();
|
||||
SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
|
||||
SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
|
||||
SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
|
||||
SDValue(Carry,0), RHS);
|
||||
|
||||
return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
|
||||
@ -370,22 +370,22 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
|
||||
|
||||
SDValue InFlag = SDValue(MulDiv, 0);
|
||||
SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
|
||||
SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
|
||||
MVT::Glue, InFlag);
|
||||
InFlag = SDValue(Lo,1);
|
||||
SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
|
||||
|
||||
if (!SDValue(Node, 0).use_empty())
|
||||
if (!SDValue(Node, 0).use_empty())
|
||||
ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
|
||||
|
||||
if (!SDValue(Node, 1).use_empty())
|
||||
if (!SDValue(Node, 1).use_empty())
|
||||
ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/// Special Muls
|
||||
case ISD::MUL:
|
||||
case ISD::MUL:
|
||||
if (Subtarget.isMips32())
|
||||
break;
|
||||
case ISD::MULHS:
|
||||
@ -394,7 +394,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
SDValue MulOp2 = Node->getOperand(1);
|
||||
|
||||
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
|
||||
SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
|
||||
SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
|
||||
MVT::Glue, MulOp1, MulOp2);
|
||||
|
||||
SDValue InFlag = SDValue(MulNode, 0);
|
||||
@ -408,7 +408,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
/// Div/Rem operations
|
||||
case ISD::SREM:
|
||||
case ISD::UREM:
|
||||
case ISD::SDIV:
|
||||
case ISD::SDIV:
|
||||
case ISD::UDIV: {
|
||||
SDValue Op1 = Node->getOperand(0);
|
||||
SDValue Op2 = Node->getOperand(1);
|
||||
@ -433,15 +433,15 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
|
||||
case ISD::ConstantFP: {
|
||||
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
|
||||
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
||||
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
||||
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
||||
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
||||
Mips::ZERO, MVT::i32);
|
||||
SDValue Undef = SDValue(
|
||||
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
|
||||
SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
|
||||
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
|
||||
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
|
||||
MVT::f64, Undef, SDValue(MTC, 0));
|
||||
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
|
||||
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
|
||||
MVT::f64, I0, SDValue(MTC, 0));
|
||||
ReplaceUses(SDValue(Node, 0), I1);
|
||||
return I1.getNode();
|
||||
@ -461,10 +461,10 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
// Other cases are autogenerated.
|
||||
break;
|
||||
|
||||
/// Handle direct and indirect calls when using PIC. On PIC, when
|
||||
/// GOT is smaller than about 64k (small code) the GA target is
|
||||
/// loaded with only one instruction. Otherwise GA's target must
|
||||
/// be loaded with 3 instructions.
|
||||
/// Handle direct and indirect calls when using PIC. On PIC, when
|
||||
/// GOT is smaller than about 64k (small code) the GA target is
|
||||
/// loaded with only one instruction. Otherwise GA's target must
|
||||
/// be loaded with 3 instructions.
|
||||
case MipsISD::JmpLink: {
|
||||
if (TM.getRelocationModel() == Reloc::PIC_) {
|
||||
unsigned LastOpNum = Node->getNumOperands()-1;
|
||||
@ -485,13 +485,13 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
|
||||
// Use load to get GOT target
|
||||
SDValue Ops[] = { Callee, GPReg, Chain };
|
||||
SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
|
||||
SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
|
||||
MVT::Other, Ops, 3), 0);
|
||||
Chain = Load.getValue(1);
|
||||
|
||||
// Call target must be on T9
|
||||
Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
|
||||
} else
|
||||
} else
|
||||
/// Indirect call
|
||||
Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
|
||||
|
||||
@ -506,14 +506,14 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
Ops.push_back(Chain.getValue(1));
|
||||
|
||||
// Emit Jump and Link Register
|
||||
SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
|
||||
SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
|
||||
&Ops[0], Ops.size());
|
||||
|
||||
// Replace Chain and InFlag
|
||||
ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
|
||||
ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
|
||||
return ResNode;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -529,7 +529,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
|
||||
return ResNode;
|
||||
}
|
||||
|
||||
/// createMipsISelDag - This pass converts a legalized DAG into a
|
||||
/// createMipsISelDag - This pass converts a legalized DAG into a
|
||||
/// MIPS-specific DAG, ready for instruction scheduling.
|
||||
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
|
||||
return new MipsDAGToDAGISel(TM);
|
||||
|
||||
@ -31,11 +31,11 @@ namespace llvm {
|
||||
|
||||
// Get the Higher 16 bits from a 32-bit immediate
|
||||
// No relation with Mips Hi register
|
||||
Hi,
|
||||
Hi,
|
||||
|
||||
// Get the Lower 16 bits from a 32-bit immediate
|
||||
// No relation with Mips Lo register
|
||||
Lo,
|
||||
Lo,
|
||||
|
||||
// Handle gp_rel (small data/bss sections) relocation.
|
||||
GPRel,
|
||||
@ -55,7 +55,7 @@ namespace llvm {
|
||||
// Floating Point Rounding
|
||||
FPRound,
|
||||
|
||||
// Return
|
||||
// Return
|
||||
Ret,
|
||||
|
||||
// MAdd/Sub nodes
|
||||
@ -69,7 +69,7 @@ namespace llvm {
|
||||
//===--------------------------------------------------------------------===//
|
||||
// TargetLowering Implementation
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
|
||||
class MipsTargetLowering : public TargetLowering {
|
||||
public:
|
||||
explicit MipsTargetLowering(MipsTargetMachine &TM);
|
||||
@ -77,7 +77,7 @@ namespace llvm {
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
/// getTargetNodeName - This method returns the name of a target specific
|
||||
/// getTargetNodeName - This method returns the name of a target specific
|
||||
// DAG node.
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
@ -87,7 +87,7 @@ namespace llvm {
|
||||
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
||||
virtual unsigned getFunctionAlignment(const Function *F) const;
|
||||
|
||||
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
private:
|
||||
// Subtarget Info
|
||||
const MipsSubtarget *Subtarget;
|
||||
@ -149,7 +149,7 @@ namespace llvm {
|
||||
ConstraintWeight getSingleConstraintMatchWeight(
|
||||
AsmOperandInfo &info, const char *constraint) const;
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass*>
|
||||
std::pair<unsigned, const TargetRegisterClass*>
|
||||
getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
EVT VT) const;
|
||||
|
||||
|
||||
@ -27,14 +27,14 @@
|
||||
def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
|
||||
SDTCisVT<1, OtherVT>]>;
|
||||
def SDT_MipsFPCmp : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
|
||||
SDTCisSameAs<1, 2>, SDTCisFP<1>,
|
||||
SDTCisSameAs<1, 2>, SDTCisFP<1>,
|
||||
SDTCisInt<3>]>;
|
||||
def SDT_MipsFPSelectCC : SDTypeProfile<1, 4, [SDTCisInt<1>, SDTCisInt<4>,
|
||||
SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
|
||||
|
||||
def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInGlue]>;
|
||||
def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
|
||||
[SDNPHasChain]>;
|
||||
def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
|
||||
[SDNPHasChain]>;
|
||||
def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
|
||||
def MipsFPSelectCC : SDNode<"MipsISD::FPSelectCC", SDT_MipsFPSelectCC>;
|
||||
|
||||
@ -54,7 +54,7 @@ def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction Class Templates
|
||||
//
|
||||
// A set of multiclasses is used to address the register usage.
|
||||
// A set of multiclasses is used to address the register usage.
|
||||
//
|
||||
// S32 - single precision in 16 32bit even fp registers
|
||||
// single precision in 32 32bit fp registers in SingleOnly mode
|
||||
@ -65,7 +65,7 @@ def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
|
||||
// Only S32 and D32 are supported right now.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass FFR1_1<bits<6> funct, string asmstr>
|
||||
multiclass FFR1_1<bits<6> funct, string asmstr>
|
||||
{
|
||||
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
|
||||
!strconcat(asmstr, ".s $fd, $fs"), []>;
|
||||
@ -74,31 +74,31 @@ multiclass FFR1_1<bits<6> funct, string asmstr>
|
||||
!strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
|
||||
}
|
||||
|
||||
multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
|
||||
multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
|
||||
{
|
||||
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
|
||||
!strconcat(asmstr, ".s $fd, $fs"),
|
||||
!strconcat(asmstr, ".s $fd, $fs"),
|
||||
[(set FGR32:$fd, (FOp FGR32:$fs))]>;
|
||||
|
||||
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
|
||||
!strconcat(asmstr, ".d $fd, $fs"),
|
||||
!strconcat(asmstr, ".d $fd, $fs"),
|
||||
[(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
|
||||
}
|
||||
|
||||
class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
|
||||
RegisterClass RcDst, string asmstr>:
|
||||
FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
|
||||
!strconcat(asmstr, " $fd, $fs"), []>;
|
||||
class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
|
||||
RegisterClass RcDst, string asmstr>:
|
||||
FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
|
||||
!strconcat(asmstr, " $fd, $fs"), []>;
|
||||
|
||||
|
||||
multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
|
||||
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
|
||||
(ins FGR32:$fs, FGR32:$ft),
|
||||
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
|
||||
(ins FGR32:$fs, FGR32:$ft),
|
||||
!strconcat(asmstr, ".s $fd, $fs, $ft"),
|
||||
[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
|
||||
|
||||
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
|
||||
(ins AFGR64:$fs, AFGR64:$ft),
|
||||
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
|
||||
(ins AFGR64:$fs, AFGR64:$ft),
|
||||
!strconcat(asmstr, ".d $fd, $fs, $ft"),
|
||||
[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
|
||||
Requires<[In32BitMode]>;
|
||||
@ -115,8 +115,8 @@ let ft = 0 in {
|
||||
defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
|
||||
defm CVTW : FFR1_1<0b100100, "cvt.w">;
|
||||
|
||||
defm FABS : FFR1_2<0b000101, "abs", fabs>;
|
||||
defm FNEG : FFR1_2<0b000111, "neg", fneg>;
|
||||
defm FABS : FFR1_2<0b000101, "abs", fabs>;
|
||||
defm FNEG : FFR1_2<0b000111, "neg", fneg>;
|
||||
defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
|
||||
|
||||
/// Convert to Single Precison
|
||||
@ -140,23 +140,23 @@ let ft = 0 in {
|
||||
def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
|
||||
|
||||
/// Convert to long signed integer
|
||||
def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
|
||||
def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
|
||||
def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
|
||||
def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
|
||||
|
||||
/// Convert to Double Precison
|
||||
def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
|
||||
def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
|
||||
def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
|
||||
|
||||
/// Convert to Double Precison
|
||||
def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
|
||||
def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
|
||||
def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
|
||||
|
||||
/// Convert to Single Precison
|
||||
def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
|
||||
def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
|
||||
def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
|
||||
}
|
||||
}
|
||||
|
||||
// The odd-numbered registers are only referenced when doing loads,
|
||||
// stores, and moves between floating-point and integer registers.
|
||||
// When defining instructions, we reference all 32-bit registers,
|
||||
// When defining instructions, we reference all 32-bit registers,
|
||||
// regardless of register aliasing.
|
||||
let fd = 0 in {
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
@ -165,7 +165,7 @@ let fd = 0 in {
|
||||
|
||||
def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
|
||||
"ctc1 $fs, $rt", []>;
|
||||
|
||||
|
||||
def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
|
||||
"mfc1 $rt, $fs", []>;
|
||||
|
||||
@ -180,18 +180,18 @@ def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
|
||||
|
||||
/// Floating Point Memory Instructions
|
||||
let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
|
||||
def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
|
||||
def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
|
||||
"ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
|
||||
|
||||
def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
|
||||
def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
|
||||
"sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
|
||||
}
|
||||
|
||||
// LWC1 and SWC1 can always be emited with odd registers.
|
||||
def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
|
||||
[(set FGR32:$ft, (load addr:$addr))]>;
|
||||
[(set FGR32:$ft, (load addr:$addr))]>;
|
||||
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
|
||||
[(store FGR32:$ft, addr:$addr)]>;
|
||||
[(store FGR32:$ft, addr:$addr)]>;
|
||||
|
||||
/// Floating-point Aritmetic
|
||||
defm FADD : FFR1_4<0x10, "add", fadd>;
|
||||
@ -202,7 +202,7 @@ defm FSUB : FFR1_4<0x01, "sub", fsub>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Branch Codes
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
|
||||
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
|
||||
// They must be kept in synch.
|
||||
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
|
||||
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
|
||||
@ -211,7 +211,7 @@ def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
|
||||
|
||||
/// Floating Point Branch of False/True (Likely)
|
||||
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
|
||||
class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
|
||||
class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
|
||||
(ins brtarget:$dst), !strconcat(asmstr, " $dst"),
|
||||
[(MipsFPBrcond op, bb:$dst, FCR31)]>;
|
||||
}
|
||||
@ -223,7 +223,7 @@ def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Flag Conditions
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
|
||||
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
|
||||
// They must be kept in synch.
|
||||
def MIPS_FCOND_F : PatLeaf<(i32 0)>;
|
||||
def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
|
||||
@ -246,8 +246,8 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
|
||||
let hasDelaySlot = 1, Defs=[FCR31] in {
|
||||
def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
|
||||
"c.$cc.s $fs, $ft",
|
||||
[(set FCR31, (MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc))]>;
|
||||
|
||||
[(set FCR31, (MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc))]>;
|
||||
|
||||
def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
|
||||
"c.$cc.d $fs, $ft",
|
||||
[(set FCR31, (MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc))]>,
|
||||
@ -258,12 +258,12 @@ let hasDelaySlot = 1, Defs=[FCR31] in {
|
||||
// Floating Point Pseudo-Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
|
||||
// For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
|
||||
// condiciton code to enable easy handling by the Custom Inserter.
|
||||
let usesCustomInserter = 1, Uses=[FCR31] in {
|
||||
class PseudoFPSelCC<RegisterClass RC, string asmstr> :
|
||||
MipsPseudo<(outs RC:$dst),
|
||||
(ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
|
||||
class PseudoFPSelCC<RegisterClass RC, string asmstr> :
|
||||
MipsPseudo<(outs RC:$dst),
|
||||
(ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
|
||||
[(set RC:$dst, (MipsFPSelectCC CPURegs:$CmpRes, RC:$T, RC:$F,
|
||||
imm:$cc))]>;
|
||||
}
|
||||
@ -278,11 +278,11 @@ def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
|
||||
|
||||
// The values to be selected and the condition test is done with fp.
|
||||
def Select_FCC_S32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_S32_f32">;
|
||||
def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
|
||||
def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
|
||||
"# MOVCCRToCCR", []>;
|
||||
def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
|
||||
"# MOVCCRToCCR", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Patterns
|
||||
@ -306,7 +306,7 @@ def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
|
||||
def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
|
||||
def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
|
||||
|
||||
let Predicates = [In32BitMode] in {
|
||||
let Predicates = [In32BitMode] in {
|
||||
def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
|
||||
def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
|
||||
}
|
||||
|
||||
@ -22,8 +22,8 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Generic Mips Format
|
||||
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
InstrItinClass itin>: Instruction
|
||||
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
InstrItinClass itin>: Instruction
|
||||
{
|
||||
field bits<32> Inst;
|
||||
|
||||
@ -32,8 +32,8 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
bits<6> opcode;
|
||||
|
||||
// Top 5 bits are the 'opcode' field
|
||||
let Inst{31-26} = opcode;
|
||||
|
||||
let Inst{31-26} = opcode;
|
||||
|
||||
dag OutOperandList = outs;
|
||||
dag InOperandList = ins;
|
||||
|
||||
@ -52,7 +52,7 @@ class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
|
||||
|
||||
class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
{
|
||||
bits<5> rd;
|
||||
bits<5> rs;
|
||||
@ -64,7 +64,7 @@ class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
|
||||
let funct = _funct;
|
||||
|
||||
let Inst{25-21} = rs;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{15-11} = rd;
|
||||
let Inst{10-6} = shamt;
|
||||
let Inst{5-0} = funct;
|
||||
@ -75,7 +75,7 @@ class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
{
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
@ -84,7 +84,7 @@ class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
let opcode = op;
|
||||
|
||||
let Inst{25-21} = rs;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{15-0} = imm16;
|
||||
}
|
||||
|
||||
@ -93,12 +93,12 @@ class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
|
||||
{
|
||||
bits<26> addr;
|
||||
|
||||
let opcode = op;
|
||||
|
||||
|
||||
let Inst{25-0} = addr;
|
||||
}
|
||||
|
||||
@ -119,9 +119,9 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
|
||||
string asmstr, list<dag> pattern> :
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
|
||||
string asmstr, list<dag> pattern> :
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
{
|
||||
bits<5> fd;
|
||||
bits<5> fs;
|
||||
@ -134,7 +134,7 @@ class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
|
||||
let fmt = _fmt;
|
||||
|
||||
let Inst{25-21} = fmt;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{15-11} = fs;
|
||||
let Inst{10-6} = fd;
|
||||
let Inst{5-0} = funct;
|
||||
@ -144,8 +144,8 @@ class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
|
||||
// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
{
|
||||
bits<5> ft;
|
||||
bits<5> base;
|
||||
@ -154,7 +154,7 @@ class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
|
||||
let opcode = op;
|
||||
|
||||
let Inst{25-21} = base;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{15-0} = imm16;
|
||||
}
|
||||
|
||||
@ -162,8 +162,8 @@ class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
|
||||
// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
|
||||
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
|
||||
{
|
||||
bits<5> fs;
|
||||
bits<5> ft;
|
||||
@ -174,7 +174,7 @@ class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
|
||||
let fmt = _fmt;
|
||||
|
||||
let Inst{25-21} = fmt;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{20-16} = ft;
|
||||
let Inst{15-11} = fs;
|
||||
let Inst{10-6} = 0;
|
||||
let Inst{5-4} = 0b11;
|
||||
|
||||
@ -36,7 +36,7 @@ static bool isZeroImm(const MachineOperand &op) {
|
||||
/// not, return 0. This predicate must return 0 if the instruction has
|
||||
/// any side effects other than loading from the stack slot.
|
||||
unsigned MipsInstrInfo::
|
||||
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
|
||||
(MI->getOpcode() == Mips::LDC1)) {
|
||||
@ -57,7 +57,7 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
/// not, return 0. This predicate must return 0 if the instruction has
|
||||
/// any side effects other than storing to the stack slot.
|
||||
unsigned MipsInstrInfo::
|
||||
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
|
||||
(MI->getOpcode() == Mips::SDC1)) {
|
||||
@ -74,7 +74,7 @@ isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
/// insertNoop - If data hazard condition is found insert the target nop
|
||||
/// instruction.
|
||||
void MipsInstrInfo::
|
||||
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
|
||||
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
|
||||
{
|
||||
DebugLoc DL;
|
||||
BuildMI(MBB, MI, DL, get(Mips::NOP));
|
||||
@ -136,7 +136,7 @@ copyPhysReg(MachineBasicBlock &MBB,
|
||||
.addReg(SrcReg, getKillRegState(KillSrc));
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
|
||||
BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
|
||||
.addReg(SrcReg, getKillRegState(KillSrc));
|
||||
@ -153,13 +153,13 @@ copyPhysReg(MachineBasicBlock &MBB,
|
||||
|
||||
void MipsInstrInfo::
|
||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const {
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
|
||||
.addImm(0).addFrameIndex(FI);
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
@ -171,7 +171,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
.addReg(SrcReg, getKillRegState(isKill))
|
||||
.addImm(0).addFrameIndex(FI);
|
||||
} else {
|
||||
const TargetRegisterInfo *TRI =
|
||||
const TargetRegisterInfo *TRI =
|
||||
MBB.getParent()->getTarget().getRegisterInfo();
|
||||
const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
|
||||
BuildMI(MBB, I, DL, get(Mips::SWC1))
|
||||
@ -189,12 +189,12 @@ void MipsInstrInfo::
|
||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, int FI,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const
|
||||
const TargetRegisterInfo *TRI) const
|
||||
{
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
|
||||
@ -202,7 +202,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
|
||||
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
|
||||
} else {
|
||||
const TargetRegisterInfo *TRI =
|
||||
const TargetRegisterInfo *TRI =
|
||||
MBB.getParent()->getTarget().getRegisterInfo();
|
||||
const unsigned *SubSet = TRI->getSubRegisters(DestReg);
|
||||
BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
|
||||
@ -218,9 +218,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
// Branch Analysis
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// GetCondFromBranchOpc - Return the Mips CC that matches
|
||||
/// GetCondFromBranchOpc - Return the Mips CC that matches
|
||||
/// the correspondent Branch instruction opcode.
|
||||
static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
|
||||
static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
|
||||
{
|
||||
switch (BrOpc) {
|
||||
default: return Mips::COND_INVALID;
|
||||
@ -231,15 +231,15 @@ static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
|
||||
case Mips::BLTZ : return Mips::COND_LZ;
|
||||
case Mips::BLEZ : return Mips::COND_LEZ;
|
||||
|
||||
// We dont do fp branch analysis yet!
|
||||
case Mips::BC1T :
|
||||
// We dont do fp branch analysis yet!
|
||||
case Mips::BC1T :
|
||||
case Mips::BC1F : return Mips::COND_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/// GetCondBranchFromCond - Return the Branch instruction
|
||||
/// opcode that matches the cc.
|
||||
unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
|
||||
unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: llvm_unreachable("Illegal condition code!");
|
||||
@ -286,9 +286,9 @@ unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
|
||||
}
|
||||
}
|
||||
|
||||
/// GetOppositeBranchCondition - Return the inverse of the specified
|
||||
/// GetOppositeBranchCondition - Return the inverse of the specified
|
||||
/// condition, e.g. turning COND_E to COND_NE.
|
||||
Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
|
||||
Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: llvm_unreachable("Illegal condition code!");
|
||||
@ -317,11 +317,11 @@ Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
|
||||
}
|
||||
}
|
||||
|
||||
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify) const
|
||||
bool AllowModify) const
|
||||
{
|
||||
// If the block has no terminators, it just falls into the block after it.
|
||||
MachineBasicBlock::iterator I = MBB.end();
|
||||
@ -335,10 +335,10 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
}
|
||||
if (!isUnpredicatedTerminator(I))
|
||||
return false;
|
||||
|
||||
|
||||
// Get the last instruction in the block.
|
||||
MachineInstr *LastInst = I;
|
||||
|
||||
|
||||
// If there is only one terminator instruction, process it.
|
||||
unsigned LastOpc = LastInst->getOpcode();
|
||||
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
|
||||
@ -370,10 +370,10 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Get the instruction before it if it is a terminator.
|
||||
MachineInstr *SecondLastInst = I;
|
||||
|
||||
|
||||
// If there are three terminators, we don't know what sort of block this is.
|
||||
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
|
||||
return true;
|
||||
@ -395,8 +395,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
FBB = LastInst->getOperand(0).getMBB();
|
||||
return false;
|
||||
}
|
||||
|
||||
// If the block ends with two unconditional branches, handle it. The last
|
||||
|
||||
// If the block ends with two unconditional branches, handle it. The last
|
||||
// one is not executed, so remove it.
|
||||
if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
|
||||
TBB = SecondLastInst->getOperand(0).getMBB();
|
||||
@ -411,7 +411,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
unsigned MipsInstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
DebugLoc DL) const {
|
||||
@ -437,10 +437,10 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
|
||||
.addMBB(TBB);
|
||||
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
// Two-way Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
||||
const TargetInstrDesc &TID = get(Opc);
|
||||
@ -456,7 +456,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
}
|
||||
|
||||
unsigned MipsInstrInfo::
|
||||
RemoveBranch(MachineBasicBlock &MBB) const
|
||||
RemoveBranch(MachineBasicBlock &MBB) const
|
||||
{
|
||||
MachineBasicBlock::iterator I = MBB.end();
|
||||
if (I == MBB.begin()) return 0;
|
||||
@ -466,31 +466,31 @@ RemoveBranch(MachineBasicBlock &MBB) const
|
||||
return 0;
|
||||
--I;
|
||||
}
|
||||
if (I->getOpcode() != Mips::J &&
|
||||
if (I->getOpcode() != Mips::J &&
|
||||
GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
||||
return 0;
|
||||
|
||||
|
||||
// Remove the branch.
|
||||
I->eraseFromParent();
|
||||
|
||||
|
||||
I = MBB.end();
|
||||
|
||||
|
||||
if (I == MBB.begin()) return 1;
|
||||
--I;
|
||||
if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
||||
return 1;
|
||||
|
||||
|
||||
// Remove the branch.
|
||||
I->eraseFromParent();
|
||||
return 2;
|
||||
}
|
||||
|
||||
/// ReverseBranchCondition - Return the inverse opcode of the
|
||||
/// ReverseBranchCondition - Return the inverse opcode of the
|
||||
/// specified Branch instruction.
|
||||
bool MipsInstrInfo::
|
||||
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
||||
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
||||
{
|
||||
assert( (Cond.size() == 3 || Cond.size() == 2) &&
|
||||
assert( (Cond.size() == 3 || Cond.size() == 2) &&
|
||||
"Invalid Mips branch condition!");
|
||||
Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
|
||||
return false;
|
||||
|
||||
@ -81,7 +81,7 @@ namespace Mips {
|
||||
COND_NE,
|
||||
COND_INVALID
|
||||
};
|
||||
|
||||
|
||||
// Turn condition code into conditional branch opcode.
|
||||
unsigned GetCondBranchFromCond(CondCode CC);
|
||||
|
||||
@ -90,7 +90,7 @@ namespace Mips {
|
||||
CondCode GetOppositeBranchCondition(Mips::CondCode CC);
|
||||
|
||||
/// MipsCCToString - Map each FP condition code to its string
|
||||
inline static const char *MipsFCCToString(Mips::CondCode CC)
|
||||
inline static const char *MipsFCCToString(Mips::CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: llvm_unreachable("Unknown condition code");
|
||||
@ -98,7 +98,7 @@ namespace Mips {
|
||||
case FCOND_T: return "f";
|
||||
case FCOND_UN:
|
||||
case FCOND_OR: return "un";
|
||||
case FCOND_EQ:
|
||||
case FCOND_EQ:
|
||||
case FCOND_NEQ: return "eq";
|
||||
case FCOND_UEQ:
|
||||
case FCOND_OGL: return "ueq";
|
||||
@ -138,25 +138,25 @@ namespace MipsII {
|
||||
enum TOF {
|
||||
//===------------------------------------------------------------------===//
|
||||
// Mips Specific MachineOperand flags.
|
||||
|
||||
|
||||
MO_NO_FLAG,
|
||||
|
||||
/// MO_GOT - Represents the offset into the global offset table at which
|
||||
/// the address the relocation entry symbol resides during execution.
|
||||
MO_GOT,
|
||||
|
||||
/// MO_GOT_CALL - Represents the offset into the global offset table at
|
||||
/// which the address of a call site relocation entry symbol resides
|
||||
/// MO_GOT_CALL - Represents the offset into the global offset table at
|
||||
/// which the address of a call site relocation entry symbol resides
|
||||
/// during execution. This is different from the above since this flag
|
||||
/// can only be present in call instructions.
|
||||
MO_GOT_CALL,
|
||||
|
||||
/// MO_GPREL - Represents the offset from the current gp value to be used
|
||||
/// MO_GPREL - Represents the offset from the current gp value to be used
|
||||
/// for the relocatable object file being produced.
|
||||
MO_GPREL,
|
||||
|
||||
/// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
|
||||
/// address.
|
||||
/// address.
|
||||
MO_ABS_HILO
|
||||
|
||||
};
|
||||
@ -181,7 +181,7 @@ public:
|
||||
/// any side effects other than loading from the stack slot.
|
||||
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
||||
int &FrameIndex) const;
|
||||
|
||||
|
||||
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
||||
/// store to a stack slot, return the virtual or physical register number of
|
||||
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
||||
@ -189,7 +189,7 @@ public:
|
||||
/// any side effects other than storing to the stack slot.
|
||||
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
|
||||
int &FrameIndex) const;
|
||||
|
||||
|
||||
/// Branch Analysis
|
||||
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
@ -220,7 +220,7 @@ public:
|
||||
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
|
||||
/// Insert nop instruction when hazard condition is found
|
||||
virtual void insertNoop(MachineBasicBlock &MBB,
|
||||
virtual void insertNoop(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const;
|
||||
|
||||
/// getGlobalBaseReg - Return a virtual register initialized with the
|
||||
|
||||
@ -26,9 +26,9 @@ def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
|
||||
SDTCisInt<4>]>;
|
||||
def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
|
||||
def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
|
||||
def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
|
||||
def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
|
||||
[SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisSameAs<2, 3>]>;
|
||||
|
||||
|
||||
@ -165,7 +165,7 @@ class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
|
||||
let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
|
||||
class MArithR<bits<6> func, string instr_asm, SDNode op> :
|
||||
FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
|
||||
!strconcat(instr_asm, "\t$rs, $rt"),
|
||||
!strconcat(instr_asm, "\t$rs, $rt"),
|
||||
[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul>;
|
||||
|
||||
// Logical
|
||||
@ -185,7 +185,7 @@ class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
|
||||
[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
|
||||
|
||||
// Shifts
|
||||
class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
|
||||
class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
|
||||
SDNode OpNode>:
|
||||
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
|
||||
!strconcat(instr_asm, "\t$dst, $b, $c"),
|
||||
@ -193,7 +193,7 @@ class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
|
||||
let rs = _rs;
|
||||
}
|
||||
|
||||
class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
|
||||
class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
|
||||
SDNode OpNode>:
|
||||
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
|
||||
!strconcat(instr_asm, "\t$dst, $b, $c"),
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
|
||||
namespace llvm {
|
||||
class Target;
|
||||
|
||||
|
||||
class MipsMCAsmInfo : public MCAsmInfo {
|
||||
public:
|
||||
explicit MipsMCAsmInfo(const Target &T, StringRef TT);
|
||||
|
||||
@ -38,7 +38,7 @@
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
||||
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
||||
const TargetInstrInfo &tii)
|
||||
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
|
||||
Subtarget(ST), TII(tii) {}
|
||||
@ -46,7 +46,7 @@ MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
||||
unsigned MipsRegisterInfo::
|
||||
getRegisterNumbering(unsigned RegEnum)
|
||||
getRegisterNumbering(unsigned RegEnum)
|
||||
{
|
||||
switch (RegEnum) {
|
||||
case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
|
||||
@ -82,30 +82,30 @@ getRegisterNumbering(unsigned RegEnum)
|
||||
case Mips::FP : case Mips::F30: case Mips::D15: return 30;
|
||||
case Mips::RA : case Mips::F31: return 31;
|
||||
default: llvm_unreachable("Unknown register number!");
|
||||
}
|
||||
}
|
||||
return 0; // Not reached
|
||||
}
|
||||
|
||||
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Callee Saved Registers methods
|
||||
// Callee Saved Registers methods
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// Mips Callee Saved Registers
|
||||
const unsigned* MipsRegisterInfo::
|
||||
getCalleeSavedRegs(const MachineFunction *MF) const
|
||||
getCalleeSavedRegs(const MachineFunction *MF) const
|
||||
{
|
||||
// Mips callee-save register range is $16-$23, $f20-$f30
|
||||
static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
|
||||
Mips::S0, Mips::S1, Mips::S2, Mips::S3,
|
||||
Mips::S0, Mips::S1, Mips::S2, Mips::S3,
|
||||
Mips::S4, Mips::S5, Mips::S6, Mips::S7,
|
||||
Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
|
||||
Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
|
||||
Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
|
||||
};
|
||||
|
||||
static const unsigned BitMode32CalleeSavedRegs[] = {
|
||||
Mips::S0, Mips::S1, Mips::S2, Mips::S3,
|
||||
Mips::S0, Mips::S1, Mips::S2, Mips::S3,
|
||||
Mips::S4, Mips::S5, Mips::S6, Mips::S7,
|
||||
Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
|
||||
};
|
||||
@ -132,11 +132,11 @@ getReservedRegs(const MachineFunction &MF) const {
|
||||
if (!Subtarget.isSingleFloat())
|
||||
for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
|
||||
Reserved.set(FReg);
|
||||
|
||||
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
// This function eliminate ADJCALLSTACKDOWN,
|
||||
// This function eliminate ADJCALLSTACKDOWN,
|
||||
// ADJCALLSTACKUP pseudo instructions
|
||||
void MipsRegisterInfo::
|
||||
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
@ -157,7 +157,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned i = 0;
|
||||
while (!MI.getOperand(i).isFI()) {
|
||||
++i;
|
||||
assert(i < MI.getNumOperands() &&
|
||||
assert(i < MI.getNumOperands() &&
|
||||
"Instr doesn't have FrameIndex operand!");
|
||||
}
|
||||
|
||||
|
||||
@ -26,7 +26,7 @@ class Type;
|
||||
struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
const MipsSubtarget &Subtarget;
|
||||
const TargetInstrInfo &TII;
|
||||
|
||||
|
||||
MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
|
||||
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
|
||||
@ -17,7 +17,7 @@ class MipsReg<string n> : Register<n> {
|
||||
let Namespace = "Mips";
|
||||
}
|
||||
|
||||
class MipsRegWithSubRegs<string n, list<Register> subregs>
|
||||
class MipsRegWithSubRegs<string n, list<Register> subregs>
|
||||
: RegisterWithSubRegs<n, subregs> {
|
||||
field bits<5> Num;
|
||||
let Namespace = "Mips";
|
||||
@ -83,7 +83,7 @@ let Namespace = "Mips" in {
|
||||
def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
|
||||
def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
|
||||
def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
|
||||
|
||||
|
||||
/// Mips Single point precision FPU Registers
|
||||
def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
|
||||
def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
|
||||
@ -117,7 +117,7 @@ let Namespace = "Mips" in {
|
||||
def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
|
||||
def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
|
||||
def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
|
||||
|
||||
|
||||
/// Mips Double point precision FPU Registers (aliased
|
||||
/// with the single precision to hold 64 bit values)
|
||||
def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
|
||||
@ -149,11 +149,11 @@ let Namespace = "Mips" in {
|
||||
// Register Classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def CPURegs : RegisterClass<"Mips", [i32], 32,
|
||||
def CPURegs : RegisterClass<"Mips", [i32], 32,
|
||||
// Return Values and Arguments
|
||||
[V0, V1, A0, A1, A2, A3,
|
||||
// Not preserved across procedure calls
|
||||
T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
|
||||
T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
|
||||
// Callee save
|
||||
S0, S1, S2, S3, S4, S5, S6, S7,
|
||||
// Reserved
|
||||
@ -173,16 +173,16 @@ def CPURegs : RegisterClass<"Mips", [i32], 32,
|
||||
|
||||
// 64bit fp:
|
||||
// * FGR64 - 32 64-bit registers
|
||||
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
||||
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
||||
//
|
||||
// 32bit fp:
|
||||
// * FGR32 - 16 32-bit even registers
|
||||
// * FGR32 - 32 32-bit registers (single float only mode)
|
||||
def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
// Return Values and Arguments
|
||||
[F0, F1, F2, F3, F12, F13, F14, F15,
|
||||
// Not preserved across procedure calls
|
||||
F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
|
||||
F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
|
||||
// Callee save
|
||||
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
|
||||
// Reserved
|
||||
@ -195,17 +195,17 @@ def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
let MethodBodies = [{
|
||||
|
||||
static const unsigned MIPS_FGR32[] = {
|
||||
Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
|
||||
Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
|
||||
Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
|
||||
Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
|
||||
Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
||||
Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
|
||||
Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
|
||||
Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
|
||||
Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
|
||||
Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
||||
Mips::F30
|
||||
};
|
||||
|
||||
static const unsigned MIPS_SVR4_FGR32[] = {
|
||||
Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
|
||||
Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
|
||||
Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
|
||||
Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
|
||||
Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
|
||||
};
|
||||
|
||||
@ -217,7 +217,7 @@ def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
if (Subtarget.isSingleFloat())
|
||||
return MIPS_FGR32;
|
||||
else
|
||||
return MIPS_SVR4_FGR32;
|
||||
return MIPS_SVR4_FGR32;
|
||||
}
|
||||
|
||||
FGR32Class::iterator
|
||||
@ -233,11 +233,11 @@ def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
}];
|
||||
}
|
||||
|
||||
def AFGR64 : RegisterClass<"Mips", [f64], 64,
|
||||
def AFGR64 : RegisterClass<"Mips", [f64], 64,
|
||||
// Return Values and Arguments
|
||||
[D0, D1, D6, D7,
|
||||
// Not preserved across procedure calls
|
||||
D2, D3, D4, D5, D8, D9,
|
||||
D2, D3, D4, D5, D8, D9,
|
||||
// Callee save
|
||||
D10, D11, D12, D13, D14,
|
||||
// Reserved
|
||||
|
||||
@ -14,7 +14,7 @@ def ALU : FuncUnit;
|
||||
def IMULDIV : FuncUnit;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction Itinerary classes used for Mips
|
||||
// Instruction Itinerary classes used for Mips
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IIAlu : InstrItinClass;
|
||||
def IILoad : InstrItinClass;
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
using namespace llvm;
|
||||
|
||||
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &FS,
|
||||
bool little) :
|
||||
bool little) :
|
||||
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
|
||||
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
|
||||
HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
|
||||
@ -33,7 +33,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &FS,
|
||||
if (TT.find("linux") == std::string::npos)
|
||||
IsLinux = false;
|
||||
|
||||
// When only the target triple is specified and is
|
||||
// When only the target triple is specified and is
|
||||
// a allegrex target, set the features. We also match
|
||||
// big and little endian allegrex cores (dont really
|
||||
// know if a big one exists)
|
||||
|
||||
@ -26,7 +26,7 @@ class MipsSubtarget : public TargetSubtarget {
|
||||
public:
|
||||
enum MipsABIEnum {
|
||||
O32, O64, N32, N64, EABI
|
||||
};
|
||||
};
|
||||
|
||||
protected:
|
||||
|
||||
@ -34,10 +34,10 @@ protected:
|
||||
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
|
||||
};
|
||||
|
||||
// Mips architecture version
|
||||
// Mips architecture version
|
||||
MipsArchEnum MipsArchVersion;
|
||||
|
||||
// Mips supported ABIs
|
||||
// Mips supported ABIs
|
||||
MipsABIEnum MipsABI;
|
||||
|
||||
// IsLittle - The target is Little Endian
|
||||
@ -61,14 +61,14 @@ protected:
|
||||
bool IsLinux;
|
||||
|
||||
/// Features related to the presence of specific instructions.
|
||||
|
||||
|
||||
// HasSEInReg - SEB and SEH (signext in register) instructions.
|
||||
bool HasSEInReg;
|
||||
|
||||
// HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
|
||||
bool HasCondMov;
|
||||
|
||||
// HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
|
||||
// HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
|
||||
// instructions.
|
||||
bool HasMulDivAdd;
|
||||
|
||||
@ -93,14 +93,14 @@ public:
|
||||
/// This constructor initializes the data members to match that
|
||||
/// of the specified triple.
|
||||
MipsSubtarget(const std::string &TT, const std::string &FS, bool little);
|
||||
|
||||
/// ParseSubtargetFeatures - Parses features string setting specified
|
||||
|
||||
/// ParseSubtargetFeatures - Parses features string setting specified
|
||||
/// subtarget options. Definition of function is auto generated by tblgen.
|
||||
std::string ParseSubtargetFeatures(const std::string &FS,
|
||||
const std::string &CPU);
|
||||
|
||||
bool isMips1() const { return MipsArchVersion == Mips1; }
|
||||
bool isMips32() const { return MipsArchVersion >= Mips32; }
|
||||
bool isMips32() const { return MipsArchVersion >= Mips32; }
|
||||
bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
|
||||
|
||||
bool isLittle() const { return IsLittle; }
|
||||
|
||||
@ -18,22 +18,22 @@ namespace llvm {
|
||||
const MCSection *SmallDataSection;
|
||||
const MCSection *SmallBSSSection;
|
||||
public:
|
||||
|
||||
|
||||
void Initialize(MCContext &Ctx, const TargetMachine &TM);
|
||||
|
||||
|
||||
|
||||
/// IsGlobalInSmallSection - Return true if this global address should be
|
||||
/// placed into small data/bss section.
|
||||
bool IsGlobalInSmallSection(const GlobalValue *GV,
|
||||
const TargetMachine &TM, SectionKind Kind)const;
|
||||
bool IsGlobalInSmallSection(const GlobalValue *GV,
|
||||
const TargetMachine &TM) const;
|
||||
|
||||
const TargetMachine &TM) const;
|
||||
|
||||
const MCSection *SelectSectionForGlobal(const GlobalValue *GV,
|
||||
SectionKind Kind,
|
||||
Mangler *Mang,
|
||||
const TargetMachine &TM) const;
|
||||
|
||||
|
||||
// TODO: Classify globals as mips wishes.
|
||||
};
|
||||
} // end namespace llvm
|
||||
|
||||
@ -14,7 +14,7 @@ using namespace llvm;
|
||||
|
||||
Target llvm::TheMipsTarget, llvm::TheMipselTarget;
|
||||
|
||||
extern "C" void LLVMInitializeMipsTargetInfo() {
|
||||
extern "C" void LLVMInitializeMipsTargetInfo() {
|
||||
RegisterTarget<Triple::mips> X(TheMipsTarget, "mips", "Mips");
|
||||
|
||||
RegisterTarget<Triple::mipsel> Y(TheMipselTarget, "mipsel", "Mipsel");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user