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When getting the number of bits necessary for addressing mode

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ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2011-10-10 07:24:23 +00:00
parent 1f104804bf
commit 8129d21396
2 changed files with 12 additions and 3 deletions
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13
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@@ -1109,11 +1109,20 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
case ARMII::AddrMode3: case ARMII::AddrMode3:
NumBits = 8; NumBits = 8;
break; break;
case ARMII::AddrModeT1_s: case ARMII::AddrModeT1_s: {
NumBits = 5; const MachineBasicBlock &MBB = *MI->getParent();
const MachineFunction &MF = *MBB.getParent();
unsigned FrameReg = ARM::SP;
if (MF.getFrameInfo()->hasVarSizedObjects())
// There are alloca()'s in this function, must reference off the frame
// pointer or base pointer instead.
FrameReg = (!hasBasePointer(MF) ?BasePtr : getFrameRegister(MF));
NumBits = (FrameReg == ARM::SP) ? 8 : 5;
Scale = 4; Scale = 4;
isSigned = false; isSigned = false;
break; break;
}
default: default:
llvm_unreachable("Unsupported addressing mode!"); llvm_unreachable("Unsupported addressing mode!");
break; break;

2
test/CodeGen/Thumb/vargs.ll
View File

@@ -1,5 +1,5 @@
; RUN: llc < %s -march=thumb ; RUN: llc < %s -march=thumb
; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 2 ; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 1
; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2 ; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2
@str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] @str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]