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With Evan's latest tblgen patch, this code is obsolete, thanks Evan!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-21 06:37:40 +00:00
parent 7d6a5155a4
commit 8151914321
1 changed files with 0 additions and 16 deletions
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16
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -944,22 +944,6 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
switch (N->getOpcode()) {
default: break;
case ISD::VECTOR_SHUFFLE:
// FIXME: This should be autogenerated from the .td file, it is here for now
// due to bugs in tblgen.
if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
SDOperand N0;
Select(N0, N->getOperand(0));
Result = CodeGenMap[Op] =
SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
N0), 0);
return;
}
assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
case ISD::SETCC:
Result = SelectSETCC(Op);
return;