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Fix a nasty bug in DAGCombine of STORE nodes.
This is very related to the bug fixed in r174431. The problem is that SelectionDAG does not include alignment in the uniquing of loads and stores. When an otherwise no-op DAGCombine would increase the alignment of a load or store, the original node would be returned (with the alignment increased), which would cause the node not to be processed by any further DAGCombines. I don't have a direct testcase for this that manifests on an in-tree target, but I did see some noise in the tests for other targets and have updated them for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232780 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9072,7 +9072,8 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
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LD->getMemoryVT(),
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LD->getMemoryVT(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isInvariant(), Align, LD->getAAInfo());
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LD->isInvariant(), Align, LD->getAAInfo());
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return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
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if (NewLoad.getNode() != N)
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return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
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}
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}
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}
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}
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}
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}
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@ -10703,11 +10704,15 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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// Try to infer better alignment information than the store already has.
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// Try to infer better alignment information than the store already has.
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if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
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if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
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if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
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if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
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if (Align > ST->getAlignment())
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if (Align > ST->getAlignment()) {
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return DAG.getTruncStore(Chain, SDLoc(N), Value,
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SDValue NewStore =
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DAG.getTruncStore(Chain, SDLoc(N), Value,
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Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
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Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
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ST->isVolatile(), ST->isNonTemporal(), Align,
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ST->isVolatile(), ST->isNonTemporal(), Align,
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ST->getAAInfo());
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ST->getAAInfo());
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if (NewStore.getNode() != N)
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return CombineTo(ST, NewStore, true);
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}
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}
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}
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}
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}
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@ -4,7 +4,7 @@
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define void @vst(i8* %m, [4 x i64] %v) {
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define void @vst(i8* %m, [4 x i64] %v) {
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entry:
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entry:
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; CHECK: vst:
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; CHECK: vst:
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; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill>
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%v0 = extractvalue [4 x i64] %v, 0
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%v0 = extractvalue [4 x i64] %v, 0
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%v1 = extractvalue [4 x i64] %v, 1
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%v1 = extractvalue [4 x i64] %v, 1
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@ -165,7 +165,7 @@ unequal:
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; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
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; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
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; DARWIN32: stw r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
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@ -1,9 +1,9 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
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define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
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define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128]
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; CHECK: lsls r[[ADDR:[0-9]+]], r[[ADDR]], #2
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; CHECK: add.w r[[ADDR:[0-9]+]], r[[SOURCE]], {{r[0-9]+}}, lsl #2
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128], r[[ADDR]]
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; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[ADDR]]:32]
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; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32]
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; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
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; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
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%val = extractelement <4 x i32> %phitmp, i32 %lane
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%val = extractelement <4 x i32> %phitmp, i32 %lane
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%r1 = insertelement <4 x i32> undef, i32 %val, i32 1
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%r1 = insertelement <4 x i32> undef, i32 %val, i32 1
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