6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-27 12:26:08 +00:00
Code Issues Projects Releases Wiki Activity

Improve code generation for vselect on SSE2:

Browse Source 
When checking the availability of instructions using the TLI, a 'promoted'
instruction IS available. It means that the value is bitcasted to another type
for which there is an operation. The correct check for the availablity of an
instruction is to check if it should be expanded.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142542 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
2011-10-19 20:43:16 +00:00
parent 12ae52767f
commit 815af82b74
2 changed files with 20 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@@ -394,9 +394,11 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
// If we can't even use the basic vector operations of // If we can't even use the basic vector operations of
// AND,OR,XOR, we will have to scalarize the op. // AND,OR,XOR, we will have to scalarize the op.
if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) || // Notice that the operation may be 'promoted' which means that it is
!TLI.isOperationLegalOrCustom(ISD::XOR, VT) || // 'bitcasted' to another type which is handled.
!TLI.isOperationLegalOrCustom(ISD::OR, VT)) if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
return DAG.UnrollVectorOp(Op.getNode()); return DAG.UnrollVectorOp(Op.getNode());
assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits() assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
@@ -421,8 +423,8 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
// Make sure that the SINT_TO_FP and SRL instructions are available. // Make sure that the SINT_TO_FP and SRL instructions are available.
if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) || if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
!TLI.isOperationLegalOrCustom(ISD::SRL, VT)) TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
return DAG.UnrollVectorOp(Op.getNode()); return DAG.UnrollVectorOp(Op.getNode());
EVT SVT = VT.getScalarType(); EVT SVT = VT.getScalarType();

17
test/CodeGen/X86/sse2-blend.ll
View File

@@ -1,8 +1,10 @@
; RUN: llc < %s -march=x86 -mcpu=yonah -promote-elements -mattr=+sse2,-sse41 | FileCheck %s ; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse41 | FileCheck %s
; currently (xor v4i32) is defined as illegal, so we scalarize the code.
; CHECK: vsel_float
; CHECK: pandn
; CHECK: pand
; CHECK: por
; CHECK: ret
define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) { define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
%A = load <4 x float>* %v1 %A = load <4 x float>* %v1
%B = load <4 x float>* %v2 %B = load <4 x float>* %v2
@@ -11,8 +13,11 @@ define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
ret void ret void
} }
; currently (xor v4i32) is defined as illegal, so we scalarize the code. ; CHECK: vsel_i32
; CHECK: pandn
; CHECK: pand
; CHECK: por
; CHECK: ret
define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) { define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
%A = load <4 x i32>* %v1 %A = load <4 x i32>* %v1
%B = load <4 x i32>* %v2 %B = load <4 x i32>* %v2