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Skip moving call address loading into callseq when targets prefer register indirect call.

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To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.

To prevent that, such moving is disabled when target favors register
indirect call.

Previous workaround disabling CALL32m/CALL64m insn selection is removed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao 2013-03-28 23:13:21 +00:00
parent d02e46be1a
commit 816f6d0ac7
4 changed files with 7 additions and 16 deletions
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4
lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -444,7 +444,9 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
if (OptLevel != CodeGenOpt::None &&
(N->getOpcode() == X86ISD::CALL ||
// Only does this when target favors doesn't favor register indirect
// call.
((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
(N->getOpcode() == X86ISD::TC_RETURN &&
// Only does this if load can be folded into TC_RETURN.
(Subtarget->is64Bit() ||

13
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2634,19 +2634,6 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
InFlag = Chain.getValue(1);
}
// Use indirect reference through register, when CALL uses a memory reference.
if (Subtarget->callRegIndirect() &&
Callee.getOpcode() == ISD::LOAD) {
const TargetRegisterClass *AddrRegClass =
getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
MachineRegisterInfo &MRI = MF.getRegInfo();
unsigned VReg = MRI.createVirtualRegister(AddrRegClass);
SDValue tempValue = DAG.getCopyFromReg(Callee,
dl, VReg, Callee.getValueType());
Chain = DAG.getCopyToReg(Chain, dl, VReg, tempValue, InFlag);
InFlag = Chain.getValue(1);
}
Ops.push_back(Chain);
Ops.push_back(Callee);

5
lib/Target/X86/X86InstrControl.td
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@ -170,7 +170,8 @@ let isCall = 1 in
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
IIC_CALL_MEM>,
Requires<[In32BitMode]>, Sched<[WriteJumpLd]>;
Requires<[In32BitMode,FavorMemIndirectCall]>,
Sched<[WriteJumpLd]>;
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
(ins i16imm:$off, i16imm:$seg),
@ -245,7 +246,7 @@ let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
IIC_CALL_MEM>,
Requires<[In64BitMode]>;
Requires<[In64BitMode,FavorMemIndirectCall]>;
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
"lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;

1
lib/Target/X86/X86InstrInfo.td
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@ -630,6 +630,7 @@ def OptForSize : Predicate<"OptForSize">;
def OptForSpeed : Predicate<"!OptForSize">;
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.