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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-21 21:29:41 +00:00
Minor cleanups to a few llvm_unreachable() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -378,12 +378,8 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
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else {
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#ifndef NDEBUG
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errs() << MO;
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#endif
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llvm_unreachable(0);
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}
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else
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llvm_unreachable("Unable to encode MachineOperand!");
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return 0;
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}
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@ -1274,12 +1274,13 @@ let isCall = 1,
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[(ARMcall GPR:$func)]>,
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Requires<[IsARM, HasV5T, IsNotDarwin]> {
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110011;
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let Inst{31-4} = 0b1110000100101111111111110011;
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let Inst{3-0} = func;
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}
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// ARMv4T
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// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
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// FIXME: x2 insn patterns like this need to be pseudo instructions.
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def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
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IIC_Br, "mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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@ -1327,7 +1328,7 @@ let isCall = 1,
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IIC_Br, "blx\t$func",
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[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110011;
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let Inst{31-4} = 0b1110000100101111111111110011;
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let Inst{3-0} = func;
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}
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@ -316,10 +316,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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.bitcastToAPInt().getHiBits(32).getLimitedValue());
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}
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#ifndef NDEBUG
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errs() << MO;
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#endif
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llvm_unreachable(0);
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llvm_unreachable("Unable to encode MCOperand!");
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return 0;
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}
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@ -421,8 +418,8 @@ getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
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}
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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return 0;
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}
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llvm_unreachable("Unsupported MCExpr type in MCOperand");
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};
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llvm_unreachable("Unsupported MCExpr type in MCOperand!");
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return 0;
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}
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