Minor cleanups to a few llvm_unreachable() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-19 00:27:09 +00:00
parent d1fadd8c5d
commit 817c1a6ddd
3 changed files with 8 additions and 14 deletions

View File

@ -378,12 +378,8 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
else {
#ifndef NDEBUG
errs() << MO;
#endif
llvm_unreachable(0);
}
else
llvm_unreachable("Unable to encode MachineOperand!");
return 0;
}

View File

@ -1274,12 +1274,13 @@ let isCall = 1,
[(ARMcall GPR:$func)]>,
Requires<[IsARM, HasV5T, IsNotDarwin]> {
bits<4> func;
let Inst{27-4} = 0b000100101111111111110011;
let Inst{31-4} = 0b1110000100101111111111110011;
let Inst{3-0} = func;
}
// ARMv4T
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
// FIXME: x2 insn patterns like this need to be pseudo instructions.
def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
@ -1327,7 +1328,7 @@ let isCall = 1,
IIC_Br, "blx\t$func",
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
bits<4> func;
let Inst{27-4} = 0b000100101111111111110011;
let Inst{31-4} = 0b1110000100101111111111110011;
let Inst{3-0} = func;
}

View File

@ -316,10 +316,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
.bitcastToAPInt().getHiBits(32).getLimitedValue());
}
#ifndef NDEBUG
errs() << MO;
#endif
llvm_unreachable(0);
llvm_unreachable("Unable to encode MCOperand!");
return 0;
}
@ -421,8 +418,8 @@ getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
}
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
return 0;
}
llvm_unreachable("Unsupported MCExpr type in MCOperand");
};
llvm_unreachable("Unsupported MCExpr type in MCOperand!");
return 0;
}