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Add support for 64-bit set-on-less-than instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -131,12 +131,16 @@ class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
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/// Arithmetic Instructions (ALU Immediate)
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/// Arithmetic Instructions (ALU Immediate)
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def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
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def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
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def DANDi : LogicI64<0x0c, "andi", and>;
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def DANDi : LogicI64<0x0c, "andi", and>;
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def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
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def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
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def DORi : LogicI64<0x0d, "ori", or>;
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def DORi : LogicI64<0x0d, "ori", or>;
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def DXORi : LogicI64<0x0e, "xori", xor>;
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def DXORi : LogicI64<0x0e, "xori", xor>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
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def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
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def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
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def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
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def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
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def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
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def DAND : LogicR64<0x24, "and", and>;
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def DAND : LogicR64<0x24, "and", and>;
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def DOR : LogicR64<0x25, "or", or>;
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def DOR : LogicR64<0x25, "or", or>;
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def DXOR : LogicR64<0x26, "xor", xor>;
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def DXOR : LogicR64<0x26, "xor", xor>;
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@ -232,3 +236,29 @@ def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
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// hi/lo relocs
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// hi/lo relocs
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def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
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// setcc patterns
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def : Pat<(seteq CPU64Regs:$lhs, CPU64Regs:$rhs),
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(SLTu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
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def : Pat<(setne CPU64Regs:$lhs, CPU64Regs:$rhs),
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(SLTu64 ZERO_64, (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs))>;
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def : Pat<(setle CPU64Regs:$lhs, CPU64Regs:$rhs),
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(XORi (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
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def : Pat<(setule CPU64Regs:$lhs, CPU64Regs:$rhs),
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(XORi (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
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def : Pat<(setgt CPU64Regs:$lhs, CPU64Regs:$rhs),
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(SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
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def : Pat<(setugt CPU64Regs:$lhs, CPU64Regs:$rhs),
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(SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
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def : Pat<(setge CPU64Regs:$lhs, CPU64Regs:$rhs),
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(XORi (SLT64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
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def : Pat<(setuge CPU64Regs:$lhs, CPU64Regs:$rhs),
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(XORi (SLTu64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
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def : Pat<(setge CPU64Regs:$lhs, immSExt16:$rhs),
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(XORi (SLTi64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
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def : Pat<(setuge CPU64Regs:$lhs, immSExt16:$rhs),
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(XORi (SLTiu64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
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@ -406,18 +406,18 @@ class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
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}
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}
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// SetCC
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
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PatFrag cond_op>:
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RegisterClass RC>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
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IIAlu>;
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
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Operand Od, PatLeaf imm_type>:
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PatLeaf imm_type, RegisterClass RC>:
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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!strconcat(instr_asm, "\t$rd, $rs, $i"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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[(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
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IIAlu>;
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IIAlu>;
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// Unconditional branch
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// Unconditional branch
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@ -615,8 +615,8 @@ let usesCustomInserter = 1 in {
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/// Arithmetic Instructions (ALU Immediate)
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
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def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
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def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
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def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def XORi : LogicI<0x0e, "xori", xor>;
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@ -627,8 +627,8 @@ def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
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def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
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def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
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def AND : LogicR<0x24, "and", and>;
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def AND : LogicR<0x24, "and", and>;
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def OR : LogicR<0x25, "or", or>;
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def OR : LogicR<0x25, "or", or>;
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def XOR : LogicR<0x26, "xor", xor>;
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def XOR : LogicR<0x26, "xor", xor>;
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