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Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123910 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
6214373fe9
commit
8197754be5
@ -3666,20 +3666,25 @@ defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
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defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
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defm STC2 : LdStCop<0b1111, 0, "stc2">;
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def MCR : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "mcr", "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{20} = 0;
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//===----------------------------------------------------------------------===//
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// Move between coprocessor and ARM core register -- for disassembly only
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//
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class MovRCopro<string opc, bit direction>
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: ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{20} = direction;
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let Inst{4} = 1;
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bits<4> Rt;
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bits<4> cop;
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bits<3> opc1;
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bits<3> opc2;
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bits<4> CRm;
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bits<4> CRn;
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let Inst{15-12} = Rt;
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let Inst{11-8} = cop;
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let Inst{23-21} = opc1;
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@ -3688,21 +3693,25 @@ def MCR : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{19-16} = CRn;
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}
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def MCR2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "mcr2\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
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def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
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class MovRCopro2<string opc, bit direction>
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: ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{20} = 0;
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let Inst{20} = direction;
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let Inst{4} = 1;
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bits<4> Rt;
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bits<4> cop;
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bits<3> opc1;
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bits<3> opc2;
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bits<4> CRm;
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bits<4> CRn;
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let Inst{15-12} = Rt;
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let Inst{11-8} = cop;
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let Inst{23-21} = opc1;
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@ -3711,63 +3720,48 @@ def MCR2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{19-16} = CRn;
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}
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def MRC : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "mrc", "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{20} = 1;
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let Inst{4} = 1;
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def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */>;
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def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */>;
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class MovRRCopro<string opc, bit direction>
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: ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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bits<4> Rt;
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bits<4> Rt2;
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bits<4> cop;
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bits<3> opc1;
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bits<3> opc2;
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bits<4> opc1;
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bits<4> CRm;
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bits<4> CRn;
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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let Inst{11-8} = cop;
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let Inst{23-21} = opc1;
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let Inst{7-5} = opc2;
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let Inst{7-4} = opc1;
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let Inst{3-0} = CRm;
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let Inst{19-16} = CRn;
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}
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def MRC2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "mrc2\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
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def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
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class MovRRCopro2<string opc, bit direction>
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: ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{20} = 1;
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let Inst{4} = 1;
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bits<4> Rt;
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bits<4> cop;
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bits<3> opc1;
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bits<3> opc2;
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bits<4> CRm;
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bits<4> CRn;
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let Inst{15-12} = Rt;
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let Inst{11-8} = cop;
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let Inst{23-21} = opc1;
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let Inst{7-5} = opc2;
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let Inst{3-0} = CRm;
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let Inst{19-16} = CRn;
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}
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, "mcrr", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0100;
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bits<4> Rt;
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bits<4> Rt2;
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bits<4> cop;
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bits<4> opc1;
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bits<4> CRm;
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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let Inst{11-8} = cop;
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@ -3775,64 +3769,8 @@ def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{3-0} = CRm;
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}
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def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, "mcrr2\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{23-20} = 0b0100;
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bits<4> Rt;
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bits<4> Rt2;
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bits<4> cop;
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bits<4> opc1;
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bits<4> CRm;
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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let Inst{11-8} = cop;
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let Inst{7-4} = opc1;
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let Inst{3-0} = CRm;
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}
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def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, "mrrc", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0101;
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bits<4> Rt;
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bits<4> Rt2;
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bits<4> cop;
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bits<4> opc1;
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bits<4> CRm;
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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let Inst{11-8} = cop;
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let Inst{7-4} = opc1;
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let Inst{3-0} = CRm;
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}
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def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, "mrrc2\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{23-20} = 0b0101;
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bits<4> Rt;
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bits<4> Rt2;
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bits<4> cop;
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bits<4> opc1;
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bits<4> CRm;
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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let Inst{11-8} = cop;
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let Inst{7-4} = opc1;
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let Inst{3-0} = CRm;
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}
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def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
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def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
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//===----------------------------------------------------------------------===//
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// Move between special register and ARM core register -- for disassembly only
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