mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
[AArch64] Generalize extract-high DUP extension to MOVI/MVNI.
These are really immediate DUPs, and suffer from the same problem
with long instructions with a high/2 variant (e.g. smull).
By extending a MOVI (or DUP, before this patch), we can avoid an ext
on the other operand of the long instruction, e.g. turning:
ext.16b v0, v0, v0, #8
movi.4h v1, #0x53
smull.4s v0, v0, v1
into:
movi.8h v1, #0x53
smull2.4s v0, v0, v1
While there, add a now-necessary combine to fold (VT NVCAST (VT x)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239799 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
d4521f1dd5
commit
819a6b7d4b
@ -7580,21 +7580,26 @@ static SDValue tryCombineFixedPointConvert(SDNode *N,
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//
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// This routine does the actual conversion of such DUPs, once outer routines
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// have determined that everything else is in order.
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// It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
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// similarly here.
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static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
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// We can handle most types of duplicate, but the lane ones have an extra
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// operand saying *which* lane, so we need to know.
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bool IsDUPLANE;
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switch (N.getOpcode()) {
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case AArch64ISD::DUP:
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IsDUPLANE = false;
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break;
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case AArch64ISD::DUPLANE8:
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case AArch64ISD::DUPLANE16:
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case AArch64ISD::DUPLANE32:
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case AArch64ISD::DUPLANE64:
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IsDUPLANE = true;
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case AArch64ISD::MOVI:
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case AArch64ISD::MOVIshift:
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case AArch64ISD::MOVIedit:
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case AArch64ISD::MOVImsl:
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case AArch64ISD::MVNIshift:
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case AArch64ISD::MVNImsl:
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break;
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default:
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// FMOV could be supported, but isn't very useful, as it would only occur
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// if you passed a bitcast' floating point immediate to an eligible long
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// integer op (addl, smull, ...).
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return SDValue();
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}
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@ -7604,17 +7609,11 @@ static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
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MVT ElementTy = NarrowTy.getVectorElementType();
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unsigned NumElems = NarrowTy.getVectorNumElements();
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MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
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MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
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SDLoc dl(N);
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SDValue NewDUP;
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if (IsDUPLANE)
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NewDUP = DAG.getNode(N.getOpcode(), dl, NewDUPVT, N.getOperand(0),
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N.getOperand(1));
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else
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NewDUP = DAG.getNode(AArch64ISD::DUP, dl, NewDUPVT, N.getOperand(0));
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy, NewDUP,
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
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DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
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DAG.getConstant(NumElems, dl, MVT::i64));
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}
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@ -8913,6 +8912,14 @@ static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
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return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
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}
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/// Get rid of unnecessary NVCASTs (that don't change the type).
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static SDValue performNVCASTCombine(SDNode *N) {
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if (N->getValueType(0) == N->getOperand(0).getValueType())
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return N->getOperand(0);
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return SDValue();
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}
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SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -8955,6 +8962,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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return performCONDCombine(N, DCI, DAG, 2, 3);
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case AArch64ISD::DUP:
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return performPostLD1Combine(N, DCI, false);
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case AArch64ISD::NVCAST:
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return performNVCASTCombine(N);
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case ISD::INSERT_VECTOR_ELT:
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return performPostLD1Combine(N, DCI, true);
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case ISD::INTRINSIC_VOID:
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@ -16,6 +16,17 @@ entry:
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ret <4 x i32> %vmull15.i.i
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}
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define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 {
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; CHECK-LABEL: test_vmull_high_n_s16_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
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; CHECK-NEXT: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
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ret <4 x i32> %vmull15.i.i
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}
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define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
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; CHECK-LABEL: test_vmull_high_n_s32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -29,6 +40,17 @@ entry:
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ret <2 x i64> %vmull9.i.i
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}
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define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 {
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; CHECK-LABEL: test_vmull_high_n_s32_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1, msl #8
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; CHECK-NEXT: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 511, i32 511>)
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ret <2 x i64> %vmull9.i.i
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}
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define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 {
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; CHECK-LABEL: test_vmull_high_n_u16:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
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@ -44,6 +66,17 @@ entry:
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ret <4 x i32> %vmull15.i.i
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}
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define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 {
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; CHECK-LABEL: test_vmull_high_n_u16_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x11, lsl #8
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; CHECK-NEXT: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 4352, i16 4352, i16 4352, i16 4352>)
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ret <4 x i32> %vmull15.i.i
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}
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define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 {
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; CHECK-LABEL: test_vmull_high_n_u32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -57,6 +90,17 @@ entry:
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ret <2 x i64> %vmull9.i.i
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}
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define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 {
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; CHECK-LABEL: test_vmull_high_n_u32_imm:
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; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].4s, #0x1, msl #8
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; CHECK-NEXT: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 4294966784, i32 4294966784>)
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ret <2 x i64> %vmull9.i.i
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}
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define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
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; CHECK-LABEL: test_vqdmull_high_n_s16:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
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@ -72,6 +116,17 @@ entry:
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ret <4 x i32> %vqdmull15.i.i
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}
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define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 {
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; CHECK-LABEL: test_vqdmull_high_n_s16_imm:
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; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].8h, #0x11, lsl #8
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; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 61183, i16 61183, i16 61183, i16 61183>)
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ret <4 x i32> %vqdmull15.i.i
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}
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define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
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; CHECK-LABEL: test_vqdmull_high_n_s32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -85,6 +140,17 @@ entry:
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ret <2 x i64> %vqdmull9.i.i
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}
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define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 {
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; CHECK-LABEL: test_vqdmull_high_n_s32_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
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; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
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ret <2 x i64> %vqdmull9.i.i
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}
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define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
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; CHECK-LABEL: test_vmlal_high_n_s16:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
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@ -101,6 +167,18 @@ entry:
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ret <4 x i32> %add.i.i
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}
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define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: test_vmlal_high_n_s16_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
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; CHECK-NEXT: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
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%add.i.i = add <4 x i32> %vmull2.i.i.i, %a
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ret <4 x i32> %add.i.i
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}
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define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
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; CHECK-LABEL: test_vmlal_high_n_s32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -115,6 +193,18 @@ entry:
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ret <2 x i64> %add.i.i
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}
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define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: test_vmlal_high_n_s32_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
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; CHECK-NEXT: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
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%add.i.i = add <2 x i64> %vmull2.i.i.i, %a
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ret <2 x i64> %add.i.i
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}
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define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
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; CHECK-LABEL: test_vmlal_high_n_u16:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
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@ -131,6 +221,18 @@ entry:
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ret <4 x i32> %add.i.i
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}
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define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: test_vmlal_high_n_u16_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
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; CHECK-NEXT: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
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%add.i.i = add <4 x i32> %vmull2.i.i.i, %a
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ret <4 x i32> %add.i.i
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}
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define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
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; CHECK-LABEL: test_vmlal_high_n_u32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -145,6 +247,18 @@ entry:
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ret <2 x i64> %add.i.i
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}
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define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: test_vmlal_high_n_u32_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
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; CHECK-NEXT: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
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%add.i.i = add <2 x i64> %vmull2.i.i.i, %a
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ret <2 x i64> %add.i.i
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}
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define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
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; CHECK-LABEL: test_vqdmlal_high_n_s16:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
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@ -161,6 +275,18 @@ entry:
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ret <4 x i32> %vqdmlal17.i.i
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}
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define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: test_vqdmlal_high_n_s16_imm:
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; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
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; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
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; CHECK-NEXT: ret
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entry:
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%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
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%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.i.i)
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ret <4 x i32> %vqdmlal17.i.i
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}
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define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
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; CHECK-LABEL: test_vqdmlal_high_n_s32:
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; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
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@ -175,6 +301,18 @@ entry:
|
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ret <2 x i64> %vqdmlal11.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
|
||||
; CHECK-LABEL: test_vqdmlal_high_n_s32_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
|
||||
; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
|
||||
%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i.i)
|
||||
ret <2 x i64> %vqdmlal11.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_s16:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
|
||||
@ -191,6 +329,18 @@ entry:
|
||||
ret <4 x i32> %sub.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_s16_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
|
||||
; CHECK-NEXT: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
|
||||
%sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i
|
||||
ret <4 x i32> %sub.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_s32:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
|
||||
@ -205,6 +355,18 @@ entry:
|
||||
ret <2 x i64> %sub.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_s32_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
|
||||
; CHECK-NEXT: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
|
||||
%sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i
|
||||
ret <2 x i64> %sub.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_u16:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
|
||||
@ -221,6 +383,18 @@ entry:
|
||||
ret <4 x i32> %sub.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_u16_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
|
||||
; CHECK-NEXT: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
|
||||
%sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i
|
||||
ret <4 x i32> %sub.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_u32:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
|
||||
@ -235,6 +409,18 @@ entry:
|
||||
ret <2 x i64> %sub.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
|
||||
; CHECK-LABEL: test_vmlsl_high_n_u32_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
|
||||
; CHECK-NEXT: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
|
||||
%sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i
|
||||
ret <2 x i64> %sub.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
|
||||
; CHECK-LABEL: test_vqdmlsl_high_n_s16:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
|
||||
@ -251,6 +437,18 @@ entry:
|
||||
ret <4 x i32> %vqdmlsl17.i.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
|
||||
; CHECK-LABEL: test_vqdmlsl_high_n_s16_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d
|
||||
; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
|
||||
%vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.i.i)
|
||||
ret <4 x i32> %vqdmlsl17.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
|
||||
; CHECK-LABEL: test_vqdmlsl_high_n_s32:
|
||||
; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
|
||||
@ -265,6 +463,18 @@ entry:
|
||||
ret <2 x i64> %vqdmlsl11.i.i
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
|
||||
; CHECK-LABEL: test_vqdmlsl_high_n_s32_imm:
|
||||
; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d
|
||||
; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%vqdmlsl9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
|
||||
%vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i.i)
|
||||
ret <2 x i64> %vqdmlsl11.i.i
|
||||
}
|
||||
|
||||
define <2 x float> @test_vmul_n_f32(<2 x float> %a, float %b) #0 {
|
||||
; CHECK-LABEL: test_vmul_n_f32:
|
||||
; CHECK-NEXT: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user