mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
Cleaned up code layout, spacing, etc. for readability purposes and to be more
consistent with the style of LLVM's code base (and itself! it's inconsistent in some places.) No functional changes were made. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
5a7a849403
commit
81b0686f09
@ -97,31 +97,28 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
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bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
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// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
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if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
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{
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miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
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miSETHI->setOperandHi32(0);
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mvec.push_back(miSETHI);
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}
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if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
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miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
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miSETHI->setOperandHi32(0);
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mvec.push_back(miSETHI);
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}
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// Set the low 10 or 12 bits in dest. This is necessary if no SETHI
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// was generated, or if the low 10 bits are non-zero.
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if (miSETHI==NULL || C & MAXLO)
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{
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if (miSETHI)
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{ // unsigned value with high-order bits set using SETHI
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miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
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miOR->setOperandLo32(1);
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}
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else
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{ // unsigned or small signed value that fits in simm13 field of OR
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assert(smallNegValue || (C & ~MAXSIMM) == 0);
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miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
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.getZeroRegNum())
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.addSImm(sC).addRegDef(dest);
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}
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mvec.push_back(miOR);
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if (miSETHI==NULL || C & MAXLO) {
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if (miSETHI) {
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// unsigned value with high-order bits set using SETHI
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miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
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miOR->setOperandLo32(1);
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} else {
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// unsigned or small signed value that fits in simm13 field of OR
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assert(smallNegValue || (C & ~MAXSIMM) == 0);
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miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
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.getZeroRegNum())
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.addSImm(sC).addRegDef(dest);
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}
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mvec.push_back(miOR);
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}
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assert((miSETHI || miOR) && "Oops, no code was generated!");
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}
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@ -266,17 +263,16 @@ CreateUIntSetInstruction(const TargetMachine& target,
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static const uint64_t lo32 = (uint32_t) ~0;
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if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
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CreateSETUWConst(target, (uint32_t) C, dest, mvec);
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else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
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{ // All high 33 (not 32) bits are 1s: sign-extension will take care
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// of high 32 bits, so use the sequence for signed int
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CreateSETSWConst(target, (int32_t) C, dest, mvec);
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}
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else if (C > lo32)
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{ // C does not fit in 32 bits
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TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
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mcfi.addTemp(tmpReg);
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CreateSETXConst(target, C, tmpReg, dest, mvec);
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}
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else if ((C & ~lo32) == ~lo32 && (C & (1 << 31))) {
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// All high 33 (not 32) bits are 1s: sign-extension will take care
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// of high 32 bits, so use the sequence for signed int
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CreateSETSWConst(target, (int32_t) C, dest, mvec);
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} else if (C > lo32) {
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// C does not fit in 32 bits
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TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
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mcfi.addTemp(tmpReg);
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CreateSETXConst(target, C, tmpReg, dest, mvec);
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}
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}
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@ -425,80 +421,72 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
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if (isa<ConstantPointerRef>(val))
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val = cast<ConstantPointerRef>(val)->getValue();
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if (isa<GlobalValue>(val))
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{
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if (isa<GlobalValue>(val)) {
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TmpInstruction* tmpReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(tmpReg);
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CreateSETXLabel(target, val, tmpReg, dest, mvec);
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} else if (valType->isIntegral()) {
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bool isValidConstant;
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unsigned opSize = target.getTargetData().getTypeSize(val->getType());
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unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
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if (! dest->getType()->isSigned()) {
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uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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if (opSize > destSize || (val->getType()->isSigned() && destSize < 8)) {
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// operand is larger than dest,
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// OR both are equal but smaller than the full register size
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// AND operand is signed, so it may have extra sign bits:
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// mask high bits
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C = C & ((1U << 8*destSize) - 1);
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}
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CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
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} else {
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int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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if (opSize > destSize)
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// operand is larger than dest: mask high bits
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C = C & ((1U << 8*destSize) - 1);
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if (opSize > destSize ||
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(opSize == destSize && !val->getType()->isSigned()))
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// sign-extend from destSize to 64 bits
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C = ((C & (1U << (8*destSize - 1)))
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? C | ~((1U << 8*destSize) - 1)
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: C);
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CreateIntSetInstruction(target, C, dest, mvec, mcfi);
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}
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else if (valType->isIntegral())
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{
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bool isValidConstant;
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unsigned opSize = target.getTargetData().getTypeSize(val->getType());
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unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
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} else {
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// Make an instruction sequence to load the constant, viz:
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// SETX <addr-of-constant>, tmpReg, addrReg
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// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
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if (! dest->getType()->isSigned())
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{
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uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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// First, create a tmp register to be used by the SETX sequence.
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TmpInstruction* tmpReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(tmpReg);
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if (opSize > destSize || (val->getType()->isSigned() && destSize < 8))
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{ // operand is larger than dest,
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// OR both are equal but smaller than the full register size
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// AND operand is signed, so it may have extra sign bits:
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// mask high bits
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C = C & ((1U << 8*destSize) - 1);
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}
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CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
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}
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else
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{
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int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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// Create another TmpInstruction for the address register
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TmpInstruction* addrReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(addrReg);
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if (opSize > destSize)
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// operand is larger than dest: mask high bits
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C = C & ((1U << 8*destSize) - 1);
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// Put the address (a symbolic name) into a register
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CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
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if (opSize > destSize ||
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(opSize == destSize && !val->getType()->isSigned()))
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// sign-extend from destSize to 64 bits
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C = ((C & (1U << (8*destSize - 1)))
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? C | ~((1U << 8*destSize) - 1)
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: C);
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// Generate the load instruction
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int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
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unsigned Opcode = ChooseLoadInstruction(val->getType());
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mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
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addSImm(zeroOffset).addRegDef(dest));
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CreateIntSetInstruction(target, C, dest, mvec, mcfi);
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}
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}
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else
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{
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// Make an instruction sequence to load the constant, viz:
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// SETX <addr-of-constant>, tmpReg, addrReg
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// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
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// First, create a tmp register to be used by the SETX sequence.
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TmpInstruction* tmpReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(tmpReg);
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// Create another TmpInstruction for the address register
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TmpInstruction* addrReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(addrReg);
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// Put the address (a symbolic name) into a register
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CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
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// Generate the load instruction
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int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
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unsigned Opcode = ChooseLoadInstruction(val->getType());
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mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
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addSImm(zeroOffset).addRegDef(dest));
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// Make sure constant is emitted to constant pool in assembly code.
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MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
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}
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// Make sure constant is emitted to constant pool in assembly code.
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MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
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}
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}
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@ -535,16 +523,16 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
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// Note that the store instruction is the same for signed and unsigned ints.
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const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
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Value* storeVal = val;
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if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy))
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{ // sign- or zero-extend respectively
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storeVal = new TmpInstruction(storeType, val);
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if (val->getType()->isSigned())
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CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
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mvec, mcfi);
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else
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CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
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mvec, mcfi);
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}
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if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
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// sign- or zero-extend respectively
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storeVal = new TmpInstruction(storeType, val);
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if (val->getType()->isSigned())
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CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
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mvec, mcfi);
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else
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CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
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mvec, mcfi);
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}
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unsigned FPReg = target.getRegInfo().getFramePointer();
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mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
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@ -622,8 +610,7 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
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const Type* resultType = dest->getType();
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MachineOpCode opCode = ChooseAddInstructionByType(resultType);
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if (opCode == V9::INVALID_OPCODE)
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{
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if (opCode == V9::INVALID_OPCODE) {
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assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
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return;
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}
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@ -632,8 +619,7 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
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// a global variable (i.e., a constant address), generate a load
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// instruction instead of an add
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//
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if (isa<Constant>(src))
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{
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if (isa<Constant>(src)) {
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unsigned int machineRegNum;
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int64_t immedValue;
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MachineOperand::MachineOperandType opType =
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@ -646,14 +632,13 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
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else if (isa<GlobalValue>(src))
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loadConstantToReg = true;
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if (loadConstantToReg)
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{ // `src' is constant and cannot fit in immed field for the ADD
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if (loadConstantToReg) {
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// `src' is constant and cannot fit in immed field for the ADD
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// Insert instructions to "load" the constant into a register
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target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
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mvec, mcfi);
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}
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else
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{ // Create an add-with-0 instruction of the appropriate type.
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} else {
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// Create an add-with-0 instruction of the appropriate type.
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// Make `src' the second operand, in case it is a constant
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// Use (unsigned long) 0 for a NULL pointer value.
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//
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@ -682,8 +667,8 @@ CreateBitExtensionInstructions(bool signExtend,
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assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
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if (numLowBits < 32)
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{ // SLL is needed since operand size is < 32 bits.
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if (numLowBits < 32) {
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// SLL is needed since operand size is < 32 bits.
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TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
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srcVal, destVal, "make32");
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mcfi.addTemp(tmpI);
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@ -97,50 +97,49 @@ FoldGetElemChain(InstrTreeNode* ptrNode, std::vector<Value*>& chainIdxVec,
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InstructionNode* ptrChild = gepNode;
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while (ptrChild && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
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ptrChild->getOpLabel() == GetElemPtrIdx))
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{
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// Child is a GetElemPtr instruction
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gepInst = cast<GetElementPtrInst>(ptrChild->getValue());
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User::op_iterator OI, firstIdx = gepInst->idx_begin();
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User::op_iterator lastIdx = gepInst->idx_end();
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bool allConstantOffsets = true;
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{
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// Child is a GetElemPtr instruction
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gepInst = cast<GetElementPtrInst>(ptrChild->getValue());
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User::op_iterator OI, firstIdx = gepInst->idx_begin();
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User::op_iterator lastIdx = gepInst->idx_end();
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bool allConstantOffsets = true;
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// The first index of every GEP must be an array index.
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assert((*firstIdx)->getType() == Type::LongTy &&
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"INTERNAL ERROR: Structure index for a pointer type!");
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// The first index of every GEP must be an array index.
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assert((*firstIdx)->getType() == Type::LongTy &&
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"INTERNAL ERROR: Structure index for a pointer type!");
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// If the last instruction had a leading non-zero index, check if the
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// current one references a sequential (i.e., indexable) type.
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// If not, the code is not type-safe and we would create an illegal GEP
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// by folding them, so don't fold any more instructions.
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//
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if (lastInstHasLeadingNonZero)
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if (! isa<SequentialType>(gepInst->getType()->getElementType()))
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break; // cannot fold in any preceding getElementPtr instrs.
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// If the last instruction had a leading non-zero index, check if the
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// current one references a sequential (i.e., indexable) type.
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// If not, the code is not type-safe and we would create an illegal GEP
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// by folding them, so don't fold any more instructions.
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//
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if (lastInstHasLeadingNonZero)
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if (! isa<SequentialType>(gepInst->getType()->getElementType()))
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break; // cannot fold in any preceding getElementPtr instrs.
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// Check that all offsets are constant for this instruction
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for (OI = firstIdx; allConstantOffsets && OI != lastIdx; ++OI)
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allConstantOffsets = isa<ConstantInt>(*OI);
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// Check that all offsets are constant for this instruction
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for (OI = firstIdx; allConstantOffsets && OI != lastIdx; ++OI)
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allConstantOffsets = isa<ConstantInt>(*OI);
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if (allConstantOffsets)
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{ // Get pointer value out of ptrChild.
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ptrVal = gepInst->getPointerOperand();
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if (allConstantOffsets) {
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// Get pointer value out of ptrChild.
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ptrVal = gepInst->getPointerOperand();
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// Remember if it has leading zero index: it will be discarded later.
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lastInstHasLeadingNonZero = ! IsZero(*firstIdx);
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// Remember if it has leading zero index: it will be discarded later.
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lastInstHasLeadingNonZero = ! IsZero(*firstIdx);
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// Insert its index vector at the start, skipping any leading [0]
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chainIdxVec.insert(chainIdxVec.begin(),
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firstIdx + !lastInstHasLeadingNonZero, lastIdx);
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// Insert its index vector at the start, skipping any leading [0]
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chainIdxVec.insert(chainIdxVec.begin(),
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firstIdx + !lastInstHasLeadingNonZero, lastIdx);
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// Mark the folded node so no code is generated for it.
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((InstructionNode*) ptrChild)->markFoldedIntoParent();
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// Mark the folded node so no code is generated for it.
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((InstructionNode*) ptrChild)->markFoldedIntoParent();
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// Get the previous GEP instruction and continue trying to fold
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ptrChild = dyn_cast<InstructionNode>(ptrChild->leftChild());
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}
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else // cannot fold this getElementPtr instr. or any preceding ones
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break;
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}
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// Get the previous GEP instruction and continue trying to fold
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ptrChild = dyn_cast<InstructionNode>(ptrChild->leftChild());
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} else // cannot fold this getElementPtr instr. or any preceding ones
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break;
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}
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// If the first getElementPtr instruction had a leading [0], add it back.
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// Note that this instruction is the *last* one successfully folded above.
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@ -186,11 +185,10 @@ GetGEPInstArgs(InstructionNode* gepNode,
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bool foldedGEPs = false;
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bool leadingNonZeroIdx = gepI && ! IsZero(*gepI->idx_begin());
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if (allConstantIndices)
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if (Value* newPtr = FoldGetElemChain(ptrChild, idxVec, leadingNonZeroIdx))
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{
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ptrVal = newPtr;
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foldedGEPs = true;
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}
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if (Value* newPtr = FoldGetElemChain(ptrChild, idxVec, leadingNonZeroIdx)) {
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ptrVal = newPtr;
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foldedGEPs = true;
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}
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// Append the index vector of the current instruction.
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// Skip the leading [0] index if preceding GEPs were folded into this.
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@ -242,12 +240,12 @@ GetMemInstArgs(InstructionNode* memInstrNode,
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InstructionNode* gepNode = NULL;
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if (isa<GetElementPtrInst>(memInst))
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gepNode = memInstrNode;
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else if (isa<InstructionNode>(ptrChild) && isa<GetElementPtrInst>(ptrVal))
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{ // Child of load/store is a GEP and memInst is its only use.
|
||||
// Use its indices and mark it as folded.
|
||||
gepNode = cast<InstructionNode>(ptrChild);
|
||||
gepNode->markFoldedIntoParent();
|
||||
}
|
||||
else if (isa<InstructionNode>(ptrChild) && isa<GetElementPtrInst>(ptrVal)) {
|
||||
// Child of load/store is a GEP and memInst is its only use.
|
||||
// Use its indices and mark it as folded.
|
||||
gepNode = cast<InstructionNode>(ptrChild);
|
||||
gepNode->markFoldedIntoParent();
|
||||
}
|
||||
|
||||
// If there are no indices, return the current pointer.
|
||||
// Else extract the pointer from the GEP and fold the indices.
|
||||
@ -268,18 +266,18 @@ ChooseBprInstruction(const InstructionNode* instrNode)
|
||||
((InstructionNode*) instrNode->leftChild())->getInstruction();
|
||||
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::BRZ; break;
|
||||
case Instruction::SetNE: opCode = V9::BRNZ; break;
|
||||
case Instruction::SetLE: opCode = V9::BRLEZ; break;
|
||||
case Instruction::SetGE: opCode = V9::BRGEZ; break;
|
||||
case Instruction::SetLT: opCode = V9::BRLZ; break;
|
||||
case Instruction::SetGT: opCode = V9::BRGZ; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
opCode = V9::INVALID_OPCODE;
|
||||
break;
|
||||
}
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::BRZ; break;
|
||||
case Instruction::SetNE: opCode = V9::BRNZ; break;
|
||||
case Instruction::SetLE: opCode = V9::BRLEZ; break;
|
||||
case Instruction::SetGE: opCode = V9::BRGEZ; break;
|
||||
case Instruction::SetLT: opCode = V9::BRLZ; break;
|
||||
case Instruction::SetGT: opCode = V9::BRGZ; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
opCode = V9::INVALID_OPCODE;
|
||||
break;
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -293,36 +291,33 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
|
||||
|
||||
bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
|
||||
|
||||
if (isSigned)
|
||||
if (isSigned) {
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::BE; break;
|
||||
case Instruction::SetNE: opCode = V9::BNE; break;
|
||||
case Instruction::SetLE: opCode = V9::BLE; break;
|
||||
case Instruction::SetGE: opCode = V9::BGE; break;
|
||||
case Instruction::SetLT: opCode = V9::BL; break;
|
||||
case Instruction::SetGT: opCode = V9::BG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
case Instruction::SetEQ: opCode = V9::BE; break;
|
||||
case Instruction::SetNE: opCode = V9::BNE; break;
|
||||
case Instruction::SetLE: opCode = V9::BLE; break;
|
||||
case Instruction::SetGE: opCode = V9::BGE; break;
|
||||
case Instruction::SetLT: opCode = V9::BL; break;
|
||||
case Instruction::SetGT: opCode = V9::BG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
else
|
||||
} else {
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::BE; break;
|
||||
case Instruction::SetNE: opCode = V9::BNE; break;
|
||||
case Instruction::SetLE: opCode = V9::BLEU; break;
|
||||
case Instruction::SetGE: opCode = V9::BCC; break;
|
||||
case Instruction::SetLT: opCode = V9::BCS; break;
|
||||
case Instruction::SetGT: opCode = V9::BGU; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
case Instruction::SetEQ: opCode = V9::BE; break;
|
||||
case Instruction::SetNE: opCode = V9::BNE; break;
|
||||
case Instruction::SetLE: opCode = V9::BLEU; break;
|
||||
case Instruction::SetGE: opCode = V9::BCC; break;
|
||||
case Instruction::SetLT: opCode = V9::BCS; break;
|
||||
case Instruction::SetGT: opCode = V9::BGU; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -334,17 +329,17 @@ ChooseBFpccInstruction(const InstructionNode* instrNode,
|
||||
MachineOpCode opCode = V9::INVALID_OPCODE;
|
||||
|
||||
switch(setCCInstr->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::FBE; break;
|
||||
case Instruction::SetNE: opCode = V9::FBNE; break;
|
||||
case Instruction::SetLE: opCode = V9::FBLE; break;
|
||||
case Instruction::SetGE: opCode = V9::FBGE; break;
|
||||
case Instruction::SetLT: opCode = V9::FBL; break;
|
||||
case Instruction::SetGT: opCode = V9::FBG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::FBE; break;
|
||||
case Instruction::SetNE: opCode = V9::FBNE; break;
|
||||
case Instruction::SetLE: opCode = V9::FBLE; break;
|
||||
case Instruction::SetGE: opCode = V9::FBGE; break;
|
||||
case Instruction::SetLT: opCode = V9::FBL; break;
|
||||
case Instruction::SetGT: opCode = V9::FBG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -367,11 +362,10 @@ GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
|
||||
|
||||
assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
|
||||
|
||||
if (lastFunction != F)
|
||||
{
|
||||
lastFunction = F;
|
||||
boolToTmpCache.clear();
|
||||
}
|
||||
if (lastFunction != F) {
|
||||
lastFunction = F;
|
||||
boolToTmpCache.clear();
|
||||
}
|
||||
|
||||
// Look for tmpI and create a new one otherwise. The new value is
|
||||
// directly written to map using the ref returned by operator[].
|
||||
@ -407,17 +401,17 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode)
|
||||
MachineOpCode opCode = V9::INVALID_OPCODE;
|
||||
|
||||
switch(instrNode->getInstruction()->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::MOVFE; break;
|
||||
case Instruction::SetNE: opCode = V9::MOVFNE; break;
|
||||
case Instruction::SetLE: opCode = V9::MOVFLE; break;
|
||||
case Instruction::SetGE: opCode = V9::MOVFGE; break;
|
||||
case Instruction::SetLT: opCode = V9::MOVFL; break;
|
||||
case Instruction::SetGT: opCode = V9::MOVFG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::MOVFE; break;
|
||||
case Instruction::SetNE: opCode = V9::MOVFNE; break;
|
||||
case Instruction::SetLE: opCode = V9::MOVFLE; break;
|
||||
case Instruction::SetGE: opCode = V9::MOVFGE; break;
|
||||
case Instruction::SetLT: opCode = V9::MOVFL; break;
|
||||
case Instruction::SetGT: opCode = V9::MOVFG; break;
|
||||
default:
|
||||
assert(0 && "Unrecognized VM instruction!");
|
||||
break;
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -441,15 +435,15 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
|
||||
valueToMove = 1;
|
||||
|
||||
switch(instrNode->getInstruction()->getOpcode())
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::MOVE; break;
|
||||
case Instruction::SetLE: opCode = V9::MOVLE; break;
|
||||
case Instruction::SetGE: opCode = V9::MOVGE; break;
|
||||
case Instruction::SetLT: opCode = V9::MOVL; break;
|
||||
case Instruction::SetGT: opCode = V9::MOVG; break;
|
||||
case Instruction::SetNE: assert(0 && "No move required!"); break;
|
||||
default: assert(0 && "Unrecognized VM instr!"); break;
|
||||
}
|
||||
{
|
||||
case Instruction::SetEQ: opCode = V9::MOVE; break;
|
||||
case Instruction::SetLE: opCode = V9::MOVLE; break;
|
||||
case Instruction::SetGE: opCode = V9::MOVGE; break;
|
||||
case Instruction::SetLT: opCode = V9::MOVL; break;
|
||||
case Instruction::SetGT: opCode = V9::MOVG; break;
|
||||
case Instruction::SetNE: assert(0 && "No move required!"); break;
|
||||
default: assert(0 && "Unrecognized VM instr!"); break;
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -460,41 +454,42 @@ ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
|
||||
MachineOpCode opCode = V9::INVALID_OPCODE;
|
||||
|
||||
switch(vopCode)
|
||||
{
|
||||
case ToFloatTy:
|
||||
if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
|
||||
opCode = V9::FITOS;
|
||||
else if (opType == Type::LongTy)
|
||||
opCode = V9::FXTOS;
|
||||
else if (opType == Type::DoubleTy)
|
||||
opCode = V9::FDTOS;
|
||||
else if (opType == Type::FloatTy)
|
||||
;
|
||||
else
|
||||
assert(0 && "Cannot convert this type to FLOAT on SPARC");
|
||||
break;
|
||||
{
|
||||
case ToFloatTy:
|
||||
if (opType == Type::SByteTy || opType == Type::ShortTy ||
|
||||
opType == Type::IntTy)
|
||||
opCode = V9::FITOS;
|
||||
else if (opType == Type::LongTy)
|
||||
opCode = V9::FXTOS;
|
||||
else if (opType == Type::DoubleTy)
|
||||
opCode = V9::FDTOS;
|
||||
else if (opType == Type::FloatTy)
|
||||
;
|
||||
else
|
||||
assert(0 && "Cannot convert this type to FLOAT on SPARC");
|
||||
break;
|
||||
|
||||
case ToDoubleTy:
|
||||
// This is usually used in conjunction with CreateCodeToCopyIntToFloat().
|
||||
// Both functions should treat the integer as a 32-bit value for types
|
||||
// of 4 bytes or less, and as a 64-bit value otherwise.
|
||||
if (opType == Type::SByteTy || opType == Type::UByteTy ||
|
||||
opType == Type::ShortTy || opType == Type::UShortTy ||
|
||||
opType == Type::IntTy || opType == Type::UIntTy)
|
||||
opCode = V9::FITOD;
|
||||
else if (opType == Type::LongTy || opType == Type::ULongTy)
|
||||
opCode = V9::FXTOD;
|
||||
else if (opType == Type::FloatTy)
|
||||
opCode = V9::FSTOD;
|
||||
else if (opType == Type::DoubleTy)
|
||||
;
|
||||
else
|
||||
assert(0 && "Cannot convert this type to DOUBLE on SPARC");
|
||||
break;
|
||||
case ToDoubleTy:
|
||||
// This is usually used in conjunction with CreateCodeToCopyIntToFloat().
|
||||
// Both functions should treat the integer as a 32-bit value for types
|
||||
// of 4 bytes or less, and as a 64-bit value otherwise.
|
||||
if (opType == Type::SByteTy || opType == Type::UByteTy ||
|
||||
opType == Type::ShortTy || opType == Type::UShortTy ||
|
||||
opType == Type::IntTy || opType == Type::UIntTy)
|
||||
opCode = V9::FITOD;
|
||||
else if (opType == Type::LongTy || opType == Type::ULongTy)
|
||||
opCode = V9::FXTOD;
|
||||
else if (opType == Type::FloatTy)
|
||||
opCode = V9::FSTOD;
|
||||
else if (opType == Type::DoubleTy)
|
||||
;
|
||||
else
|
||||
assert(0 && "Cannot convert this type to DOUBLE on SPARC");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -507,22 +502,17 @@ ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType)
|
||||
assert((opType == Type::FloatTy || opType == Type::DoubleTy)
|
||||
&& "This function should only be called for FLOAT or DOUBLE");
|
||||
|
||||
if (tid==Type::UIntTyID)
|
||||
{
|
||||
assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
|
||||
" into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
|
||||
}
|
||||
else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
|
||||
tid==Type::UByteTyID || tid==Type::UShortTyID)
|
||||
{
|
||||
opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
|
||||
}
|
||||
else if (tid==Type::LongTyID || tid==Type::ULongTyID)
|
||||
{
|
||||
if (tid == Type::UIntTyID) {
|
||||
assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
|
||||
" into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
|
||||
} else if (tid == Type::SByteTyID || tid == Type::ShortTyID ||
|
||||
tid == Type::IntTyID || tid == Type::UByteTyID ||
|
||||
tid == Type::UShortTyID) {
|
||||
opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
|
||||
} else if (tid == Type::LongTyID || tid == Type::ULongTyID) {
|
||||
opCode = (opType == Type::FloatTy)? V9::FSTOX : V9::FDTOX;
|
||||
}
|
||||
else
|
||||
assert(0 && "Should not get here, Mo!");
|
||||
} else
|
||||
assert(0 && "Should not get here, Mo!");
|
||||
|
||||
return opCode;
|
||||
}
|
||||
@ -611,11 +601,11 @@ CreateAddConstInstruction(const InstructionNode* instrNode)
|
||||
// instead of an FADD (1 vs 3 cycles). There is no integer MOV.
|
||||
//
|
||||
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
|
||||
double dval = FPC->getValue();
|
||||
if (dval == 0.0)
|
||||
minstr = CreateMovFloatInstruction(instrNode,
|
||||
instrNode->getInstruction()->getType());
|
||||
}
|
||||
double dval = FPC->getValue();
|
||||
if (dval == 0.0)
|
||||
minstr = CreateMovFloatInstruction(instrNode,
|
||||
instrNode->getInstruction()->getType());
|
||||
}
|
||||
|
||||
return minstr;
|
||||
}
|
||||
@ -626,17 +616,16 @@ ChooseSubInstructionByType(const Type* resultType)
|
||||
{
|
||||
MachineOpCode opCode = V9::INVALID_OPCODE;
|
||||
|
||||
if (resultType->isInteger() || isa<PointerType>(resultType))
|
||||
{
|
||||
if (resultType->isInteger() || isa<PointerType>(resultType)) {
|
||||
opCode = V9::SUB;
|
||||
}
|
||||
else
|
||||
} else {
|
||||
switch(resultType->getPrimitiveID())
|
||||
{
|
||||
case Type::FloatTyID: opCode = V9::FSUBS; break;
|
||||
case Type::DoubleTyID: opCode = V9::FSUBD; break;
|
||||
default: assert(0 && "Invalid type for SUB instruction"); break;
|
||||
}
|
||||
{
|
||||
case Type::FloatTyID: opCode = V9::FSUBS; break;
|
||||
case Type::DoubleTyID: opCode = V9::FSUBD; break;
|
||||
default: assert(0 && "Invalid type for SUB instruction"); break;
|
||||
}
|
||||
}
|
||||
|
||||
return opCode;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user