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The powerpc is now gone. However it is now just known as the Skeleton target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14877 91177308-0d34-0410-b5e6-96231b3b80d8
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//===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// PowerPC back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_POWERPC_H
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#define TARGET_POWERPC_H
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#include <iosfwd>
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namespace llvm {
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class FunctionPass;
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class TargetMachine;
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// Here is where you would define factory methods for powerpc-specific
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// passes. For example:
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// FunctionPass *createPowerPCSimpleInstructionSelector (TargetMachine &TM);
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// FunctionPass *createPowerPCCodePrinterPass(std::ostream &OS,
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// TargetMachine &TM);
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} // end namespace llvm;
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// Defines symbolic names for PowerPC registers. This defines a mapping from
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// register name to register number.
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//
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#include "PowerPCGenRegisterNames.inc"
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// Defines symbolic names for the PowerPC instructions.
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//
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#include "PowerPCGenInstrNames.inc"
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#endif
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//===- PowerPCInstrInfo.td - Describe the PowerPC Instruction Set -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class Format<bits<4> val> {
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bits<4> Value = val;
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}
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// All of the PowerPC instruction formats, plus a pseudo-instruction format:
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def Pseudo : Format<0>;
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def IForm : Format<1>;
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def BForm : Format<2>;
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def SCForm : Format<3>;
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def DForm : Format<4>;
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def XForm : Format<5>;
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def XLForm : Format<6>;
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def XFXForm : Format<7>;
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def XFLForm : Format<8>;
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def XOForm : Format<9>;
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def AForm : Format<10>;
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def MForm : Format<11>;
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class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
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let Namespace = "PowerPC";
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let Name = nm;
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bits<6> Opcode = opcd;
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Format Form = f;
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bits<4> FormBits = Form.Value;
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}
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// Pseudo-instructions:
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def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
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def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
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def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
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def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
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//===- PowerPCJITInfo.h - PowerPC impl. of the JIT interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetJITInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPCJITINFO_H
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#define POWERPCJITINFO_H
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#include "llvm/Target/TargetJITInfo.h"
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namespace llvm {
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class TargetMachine;
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class IntrinsicLowering;
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class PowerPCJITInfo : public TargetJITInfo {
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TargetMachine &TM;
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public:
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PowerPCJITInfo(TargetMachine &tm) : TM(tm) {}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this
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/// is not supported for this target.
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///
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virtual void addPassesToJITCompile(FunctionPassManager &PM);
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/// replaceMachineCodeForFunction - Make it so that calling the function
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/// whose machine code is at OLD turns into a call to NEW, perhaps by
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/// overwriting OLD with a branch to NEW. This is used for self-modifying
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/// code.
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///
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virtual void replaceMachineCodeForFunction(void *Old, void *New);
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/// getJITStubForFunction - Create or return a stub for the specified
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/// function. This stub acts just like the specified function, except that
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/// it allows the "address" of the function to be taken without having to
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/// generate code for it.
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virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
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};
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}
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#endif
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//===- PowerPCReg.td - Describe the PowerPC Register File -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the PowerPC register file in Tablegen format.
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//
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//===----------------------------------------------------------------------===//
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class PPCReg : Register {
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let Namespace = "PowerPC";
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}
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// We identify all our registers with a 5-bit ID, for consistency's sake.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num> : PPCReg {
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field bits<5> Num = num;
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}
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// SPR - One of the 32-bit special-purpose registers
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class SPR<bits<5> num> : PPCReg {
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field bits<5> Num = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num> : PPCReg {
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field bits<5> Num = num;
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<5> num> : PPCReg {
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field bits<5> Num = num;
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}
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// General-purpose registers
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def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
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def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
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def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
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def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
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def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
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def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
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def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
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def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
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// Floating-point registers
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def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
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def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
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def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
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def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
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def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
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def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
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def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
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def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
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// Condition registers
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def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
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def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
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// Floating-point status and control register
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def FPSCR : SPR<0>;
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// fiXed-point Exception Register? :-)
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def XER : SPR<1>;
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// Link register
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def LR : SPR<2>;
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// Count register
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def CTR : SPR<3>;
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// These are the "time base" registers which are read-only in user mode.
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def TBL : SPR<4>;
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def TBU : SPR<5>;
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/// Register classes: one for floats and another for non-floats.
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def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
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R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
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def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPCTargetMachine.h"
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#include "PowerPC.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<PowerPCTargetMachine> X("powerpc", " PowerPC (experimental)");
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}
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/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
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///
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PowerPCTargetMachine::PowerPCTargetMachine(const Module &M,
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IntrinsicLowering *IL)
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: TargetMachine("PowerPC", IL, true, 4, 4, 4, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4), JITInfo(*this) {
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}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// <insert instruction selector passes here>
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// <insert assembly code output passes here>
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PM.add(createMachineCodeDeleter());
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return true; // change to `return false' when this actually works.
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// <insert instruction selector passes here>
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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}
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