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[mips][mips64r6] Add bc[12](eq|ne)z

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Summary: Depends on D3691

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-05-21 12:56:39 +00:00
parent 3046dcbce4
commit 820861536c
5 changed files with 91 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@@ -195,6 +195,11 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,
@@ -846,6 +851,18 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,

29
lib/Target/Mips/Mips32r6InstrFormats.td
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@@ -24,6 +24,7 @@ class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
//===----------------------------------------------------------------------===//
def OPGROUP_COP1 { bits<6> Value = 0b010001; }
def OPGROUP_COP2 { bits<6> Value = 0b010010; }
def OPGROUP_AUI { bits<6> Value = 0b001111; }
def OPGROUP_DAUI { bits<6> Value = 0b011101; }
def OPGROUP_PCREL { bits<6> Value = 0b111011; }
@@ -45,6 +46,10 @@ def OPCODE5_ALUIPC : OPCODE5<0b11111>;
def OPCODE5_AUIPC : OPCODE5<0b11110>;
def OPCODE5_DAHI : OPCODE5<0b00110>;
def OPCODE5_DATI : OPCODE5<0b11110>;
def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
class OPCODE6<bits<6> Val> {
bits<6> Value = Val;
@@ -138,6 +143,30 @@ class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
let Inst{5-0} = funct;
}
class COP1_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
bits<5> ft;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = OPGROUP_COP1.Value;
let Inst{25-21} = Operation.Value;
let Inst{20-16} = ft;
let Inst{15-0} = offset;
}
class COP2_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
bits<5> ct;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = OPGROUP_COP2.Value;
let Inst{25-21} = Operation.Value;
let Inst{20-16} = ct;
let Inst{15-0} = offset;
}
class PCREL16_FM<OPCODE5 Operation> : MipsR6Inst {
bits<5> rs;
bits<16> imm;

33
lib/Target/Mips/Mips32r6InstrInfo.td
View File

@@ -107,6 +107,11 @@ class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>;
class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
@@ -326,6 +331,26 @@ class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
dag OutOperandList = (outs);
string AsmString = instr_asm;
bit hasDelaySlot = 1;
}
class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
dag OutOperandList = (outs);
string AsmString = instr_asm;
bit hasDelaySlot = 1;
}
class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
RegisterOperand GPROpnd> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
@@ -484,10 +509,10 @@ def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
def BC1EQZ;
def BC1NEZ;
def BC2EQZ;
def BC2NEZ;
def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;