From 8213c96655e955a0b63b05580bc2f6a55be26083 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 16 Sep 2011 20:50:13 +0000 Subject: [PATCH] Thumb2 assembly parsing and encoding for STMIA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb2.td | 3 ++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 ++++++++- test/MC/ARM/basic-thumb2-instructions.s | 38 +++++++++++++++++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 1d86a2a80b8..4d15b0201dd 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3861,3 +3861,6 @@ def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; +// STM w/o the .w suffix. +def : t2InstAlias<"stm${p} $Rn, $regs", + (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 51651e4b264..149c46f28c5 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3679,7 +3679,7 @@ validateInstruction(MCInst &Inst, } case ARM::tSTMIA_UPD: { bool listContainsBase; - if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase)) + if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) return Error(Operands[4]->getStartLoc(), "registers must be in range r0-r7"); break; @@ -3778,6 +3778,19 @@ processInstruction(MCInst &Inst, } break; } + case ARM::tSTMIA_UPD: { + // If the register list contains any high registers, we need to use + // the 32-bit encoding instead if we're in Thumb2. Otherwise, this + // should have generated an error in validateInstruction(). + unsigned Rn = Inst.getOperand(0).getReg(); + bool listContainsBase; + if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { + // 16-bit encoding isn't sufficient. Switch to the 32-bit version. + assert (isThumbTwo()); + Inst.setOpcode(ARM::t2STMIA_UPD); + } + break; + } case ARM::t2MOVi: { // If we can use the 16-bit encoding and the user didn't explicitly // request the 32-bit variant, transform it here. diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 5117bf8b702..d0fdb05295f 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -2108,6 +2108,44 @@ _func: @ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xc1,0xfa,0x02,0xf5] +@------------------------------------------------------------------------------ +@ STMIA +@------------------------------------------------------------------------------ + stmia.w r4, {r4, r5, r8, r9} + stmia.w r4, {r5, r6} + stmia.w r5!, {r3, r8} + stm.w r4, {r4, r5, r8, r9} + stm.w r4, {r5, r6} + stm.w r5!, {r3, r8} + stm.w r5!, {r1, r2} + stm.w r2, {r1, r2} + + stmia r4, {r4, r5, r8, r9} + stmia r4, {r5, r6} + stmia r5!, {r3, r8} + stm r4, {r4, r5, r8, r9} + stm r4, {r5, r6} + stm r5!, {r3, r8} + stmea r5!, {r3, r8} + +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r5!, {r1, r2} @ encoding: [0xa5,0xe8,0x06,0x00] +@ CHECK: stm.w r2, {r1, r2} @ encoding: [0x82,0xe8,0x06,0x00] + +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] + + @------------------------------------------------------------------------------ @ SUB (register) @------------------------------------------------------------------------------