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Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-23 17:51:38 +00:00
parent 20a05be15e
commit 82265a2c72
2 changed files with 12 additions and 3 deletions
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12
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2392,9 +2392,15 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = Success; DecodeStatus S = Success;
if (Inst.getOpcode() != ARM::t2PLDs) { switch (Inst.getOpcode()) {
unsigned Rt = fieldFromInstruction32(Insn, 12, 4); case ARM::t2PLDs:
CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); case ARM::t2PLDWs:
case ARM::t2PLIs:
break;
default: {
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
}
} }
unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4);

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -292,3 +292,6 @@
# CHECK: uxtb16 r9, r12, ror #16 # CHECK: uxtb16 r9, r12, ror #16
0x3f 0xfa 0xec 0xf9 0x3f 0xfa 0xec 0xf9
# CHECK: pldw [r11, r12, lsl #2]
0x3b 0xf8 0x2c 0xf0