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Two sets of changes. Sorry they are intermingled.

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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-11-03 00:45:17 +00:00
parent 41957f6eb2
commit 8239daf7c8
17 changed files with 296 additions and 165 deletions
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22
lib/Target/ARM/ARMBaseInstrInfo.h
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@@ -318,18 +318,20 @@ public:
const MachineFunction &MF) const;
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
unsigned NumInstrs,
unsigned NumCyles, unsigned ExtraPredCycles,
float Prob, float Confidence) const;
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
MachineBasicBlock &FMBB,unsigned NumF,
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumT, unsigned ExtraT,
MachineBasicBlock &FMBB,
unsigned NumF, unsigned ExtraF,
float Probability, float Confidence) const;
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
unsigned NumInstrs,
unsigned NumCyles,
float Probability,
float Confidence) const {
return NumInstrs == 1;
return NumCyles == 1;
}
/// AnalyzeCompare - For a comparison instruction, return the source register
@@ -345,8 +347,8 @@ public:
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const;
virtual unsigned getNumMicroOps(const MachineInstr *MI,
const InstrItineraryData *ItinData) const;
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const;
virtual
int getOperandLatency(const InstrItineraryData *ItinData,
@@ -379,6 +381,12 @@ private:
const TargetInstrDesc &UseTID,
unsigned UseIdx, unsigned UseAlign) const;
int getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI, unsigned *PredCost = 0) const;
int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const;
bool hasHighOperandLatency(const InstrItineraryData *ItinData,
const MachineRegisterInfo *MRI,
const MachineInstr *DefMI, unsigned DefIdx,