[AArch64] This is a work in progress to provide a machine description

for the Cortex-A53 subtarget in the AArch64 backend.

This patch lays the ground work to annotate each AArch64 instruction
(no NEON yet) with a list of SchedReadWrite types. The patch also
provides the Cortex-A53 processor resources, maps those the the default
SchedReadWrites, and provides basic latency. NEON support will be added
in a subsequent patch with proper forwarding logic.

Verification was done by setting the pre-RA scheduler to linearize to
better gauge the effect of the MIScheduler. Even without modeling the
forward logic, the results show a modest improvement for Cortex-A53.

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202767 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64.td

@@ -41,13 +41,20 @@ class ProcNoItin<string Name, list<SubtargetFeature> Features>
 
 def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
 
-def : ProcNoItin<"cortex-a53",      [FeatureFPARMv8,
-                                    FeatureNEON,
-                                    FeatureCrypto]>;
+def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
+                                   "Cortex-A53 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto]>;
 
-def : ProcNoItin<"cortex-a57",      [FeatureFPARMv8,
-                                    FeatureNEON,
-                                    FeatureCrypto]>;
+def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
+                                   "Cortex-A57 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto]>;
+
+def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
+def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

lib/Target/AArch64/AArch64Schedule.td

@@ -7,4 +7,66 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// Generic processor itineraries for legacy compatibility.
+
 def GenericItineraries : ProcessorItineraries<[], [], []>;
+
+
+//===----------------------------------------------------------------------===//
+// Base SchedReadWrite types
+
+// Basic ALU
+def WriteALU : SchedWrite;  // Generic: may contain shift and/or ALU operation
+def WriteALUs : SchedWrite; // Shift only with no ALU operation
+def ReadALU : SchedRead;    // Operand not needed for shifting
+def ReadALUs : SchedRead;   // Operand needed for shifting
+
+// Multiply with optional accumulate
+def WriteMAC : SchedWrite;
+def ReadMAC : SchedRead;
+
+// Compares
+def WriteCMP : SchedWrite;
+def ReadCMP : SchedRead;
+
+// Division
+def WriteDiv : SchedWrite;
+def ReadDiv : SchedRead;
+
+// Loads
+def WriteLd : SchedWrite;
+def WritePreLd : SchedWrite;
+def ReadLd : SchedRead;
+def ReadPreLd : SchedRead;
+
+// Branches
+def WriteBr : SchedWrite;
+def WriteBrL : SchedWrite;
+def ReadBr : SchedRead;
+
+// Floating Point ALU
+def WriteFPALU : SchedWrite;
+def ReadFPALU : SchedRead;
+
+// Floating Point MAC, Mul, Div, Sqrt
+//   Most processors will simply send all of these down a dedicated pipe, but
+//   they're explicitly seperated here for flexibility of modeling later. May
+//   consider consolidating them into a single WriteFPXXXX type in the future.
+def WriteFPMAC : SchedWrite;
+def WriteFPMul : SchedWrite;
+def WriteFPDiv : SchedWrite;
+def WriteFPSqrt : SchedWrite;
+def ReadFPMAC : SchedRead;
+def ReadFPMul : SchedRead;
+def ReadFPDiv : SchedRead;
+def ReadFPSqrt : SchedRead;
+
+// Noop
+def WriteNoop : SchedWrite;
+
+
+//===----------------------------------------------------------------------===//
+// Subtarget specific Machine Models.
+
+include "AArch64ScheduleA53.td"

lib/Target/AArch64/AArch64ScheduleA53.td

@@ -0,0 +1,130 @@
+//=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the itinerary class data for the ARM Cortex A53 processors.
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the simpler per-operand machine model.
+// This works with MachineScheduler. See MCSchedModel.h for details.
+
+// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
+def CortexA53Model : SchedMachineModel {
+  let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
+  let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
+  let LoadLatency = 2; // Optimistic load latency assuming bypass.
+                       // This is overriden by OperandCycles if the
+                       // Itineraries are queried instead.
+  let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
+                             // Specification - Instruction Timings"
+                             // v 1.0 Spreadsheet
+}
+
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available.
+
+// Modeling each pipeline as a ProcResource using the default BufferSize = -1.
+// Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
+// current configuration performs better with the basic latencies provided so
+// far. Will revisit BufferSize once the latency information is more accurate.
+
+let SchedModel = CortexA53Model in {
+
+def A53UnitALU    : ProcResource<2>;                        // Int ALU
+def A53UnitMAC    : ProcResource<1>;                        // Int MAC
+def A53UnitDiv    : ProcResource<1>;                        // Int Division
+def A53UnitLdSt   : ProcResource<1>;                        // Load/Store
+def A53UnitB      : ProcResource<1>;                        // Branch
+def A53UnitFPALU  : ProcResource<1>;                        // FP ALU
+def A53UnitFPMDS  : ProcResource<1>;                        // FP Mult/Div/Sqrt
+
+
+//===----------------------------------------------------------------------===//
+// Subtarget-specific SchedWrite types which both map the ProcResources and
+// set the latency.
+
+// Issue - Every instruction must consume an A53WriteIssue. Optionally,
+//         instructions that cannot be dual-issued will also include the
+//         A53WriteIssue2nd in their SchedRW list. That second WriteRes will
+//         ensure that a second issue slot is consumed.
+def A53WriteIssue : SchedWriteRes<[]>;
+def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
+
+// ALU - These are reduced to 1 despite a true latency of 4 in order to easily
+//       model forwarding logic. Once forwarding is properly modelled, then
+//       they'll be corrected.
+def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }
+def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }
+def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }
+
+// MAC
+def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
+
+// Div
+def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
+
+// Load
+def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
+def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
+
+// Branch
+def : WriteRes<WriteBr, [A53UnitB]>;
+def : WriteRes<WriteBrL, [A53UnitB]>;
+
+// FP ALU
+def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }
+
+// FP MAC, Mul, Div, Sqrt
+//   Using Double Precision numbers for now as a worst case. Additionally, not
+//   modeling the exact hazard but instead treating the whole pipe as a hazard.
+//   As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
+//   have a total latency of 33 and 32 respectively but only a hazard of 29 and
+//   28 (double-prescion example).
+def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }
+def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }
+def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;
+                                             let ResourceCycles = [29]; }
+def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;
+                                              let ResourceCycles = [28]; }
+
+
+//===----------------------------------------------------------------------===//
+// Subtarget-specific SchedRead types.
+
+// No forwarding defined for ReadALU yet.
+def : ReadAdvance<ReadALU, 0>;
+
+// No forwarding defined for ReadCMP yet.
+def : ReadAdvance<ReadCMP, 0>;
+
+// No forwarding defined for ReadBr yet.
+def : ReadAdvance<ReadBr, 0>;
+
+// No forwarding defined for ReadMAC yet.
+def : ReadAdvance<ReadMAC, 0>;
+
+// No forwarding defined for ReadDiv yet.
+def : ReadAdvance<ReadDiv, 0>;
+
+// No forwarding defined for ReadLd, ReadPreLd yet.
+def : ReadAdvance<ReadLd, 0>;
+def : ReadAdvance<ReadPreLd, 0>;
+
+// No forwarding defined for ReadFPALU yet.
+def : ReadAdvance<ReadFPALU, 0>;
+
+// No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
+def : ReadAdvance<ReadFPMAC, 0>;
+def : ReadAdvance<ReadFPMul, 0>;
+def : ReadAdvance<ReadFPDiv, 0>;
+def : ReadAdvance<ReadFPSqrt, 0>;
+
+}

lib/Target/AArch64/AArch64Subtarget.h

@@ -29,6 +29,11 @@ class GlobalValue;
 class AArch64Subtarget : public AArch64GenSubtargetInfo {
   virtual void anchor();
 protected:
+  enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
+
+  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
+  ARMProcFamilyEnum ARMProcFamily;
+
   bool HasFPARMv8;
   bool HasNEON;
   bool HasCrypto;