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teach getClass what a condition reg is
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23105 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,10 +44,12 @@ PPC32RegisterInfo::PPC32RegisterInfo()
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}
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}
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static const TargetRegisterClass *getClass(unsigned SrcReg) {
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static const TargetRegisterClass *getClass(unsigned SrcReg) {
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if (PPC32::GPRCRegisterClass->contains(SrcReg))
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return PPC32::GPRCRegisterClass;
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if (PPC32::FPRCRegisterClass->contains(SrcReg))
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if (PPC32::FPRCRegisterClass->contains(SrcReg))
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return PPC32::FPRCRegisterClass;
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return PPC32::FPRCRegisterClass;
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assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
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assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC");
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return PPC32::GPRCRegisterClass;
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return PPC32::CRRCRegisterClass;
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}
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}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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static unsigned getIdx(const TargetRegisterClass *RC) {
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@ -101,7 +103,7 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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static const unsigned Opcode[] = {
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static const unsigned Opcode[] = {
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
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};
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};
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const TargetRegisterClass *RegClass = getClass(SrcReg);
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const TargetRegisterClass *RegClass = getClass(DestReg);
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unsigned OC = Opcode[getIdx(RegClass)];
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unsigned OC = Opcode[getIdx(RegClass)];
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if (DestReg == PPC::LR) {
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if (DestReg == PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
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addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
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