mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
teach getClass what a condition reg is
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
5087daac23
commit
82972705df
@ -44,10 +44,12 @@ PPC32RegisterInfo::PPC32RegisterInfo()
|
|||||||
}
|
}
|
||||||
|
|
||||||
static const TargetRegisterClass *getClass(unsigned SrcReg) {
|
static const TargetRegisterClass *getClass(unsigned SrcReg) {
|
||||||
|
if (PPC32::GPRCRegisterClass->contains(SrcReg))
|
||||||
|
return PPC32::GPRCRegisterClass;
|
||||||
if (PPC32::FPRCRegisterClass->contains(SrcReg))
|
if (PPC32::FPRCRegisterClass->contains(SrcReg))
|
||||||
return PPC32::FPRCRegisterClass;
|
return PPC32::FPRCRegisterClass;
|
||||||
assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
|
assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC");
|
||||||
return PPC32::GPRCRegisterClass;
|
return PPC32::CRRCRegisterClass;
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned getIdx(const TargetRegisterClass *RC) {
|
static unsigned getIdx(const TargetRegisterClass *RC) {
|
||||||
@ -101,7 +103,7 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|||||||
static const unsigned Opcode[] = {
|
static const unsigned Opcode[] = {
|
||||||
PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
|
PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
|
||||||
};
|
};
|
||||||
const TargetRegisterClass *RegClass = getClass(SrcReg);
|
const TargetRegisterClass *RegClass = getClass(DestReg);
|
||||||
unsigned OC = Opcode[getIdx(RegClass)];
|
unsigned OC = Opcode[getIdx(RegClass)];
|
||||||
if (DestReg == PPC::LR) {
|
if (DestReg == PPC::LR) {
|
||||||
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
|
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
|
||||||
|
Loading…
Reference in New Issue
Block a user