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Avoid making unneeded load/mod/store transformation which can hurt performance.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29952 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-08-29 06:44:17 +00:00
parent 1efba0ecb4
commit 82a35b34fb
1 changed files with 10 additions and 5 deletions
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15
lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -80,6 +80,9 @@ namespace {
Statistic<>
NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
Statistic<>
NumLoadMoved("x86-codegen", "Number of loads moved below TokenFactor");
//===--------------------------------------------------------------------===//
/// ISel - X86 specific code to select X86 machine instructions for
/// SelectionDAG operations.
@ -313,8 +316,6 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
switch (Opcode) {
case ISD::ADD:
case ISD::MUL:
case ISD::FADD:
case ISD::FMUL:
case ISD::AND:
case ISD::OR:
case ISD::XOR:
@ -329,7 +330,8 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
std::swap(N10, N11);
}
RModW = RModW && N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
N10.getOperand(1) == N2;
(N10.getOperand(1) == N2) &&
(N10.Val->getValueType(0) == N1.getValueType());
if (RModW)
Load = N10;
break;
@ -347,15 +349,18 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
SDOperand N10 = N1.getOperand(0);
if (N10.Val->getOpcode() == ISD::LOAD)
RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
N10.getOperand(1) == N2;
(N10.getOperand(1) == N2) &&
(N10.Val->getValueType(0) == N1.getValueType());
if (RModW)
Load = N10;
break;
}
}
if (RModW)
if (RModW) {
MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
++NumLoadMoved;
}
}
}