6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30892 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-10-11 21:06:01 +00:00
parent af9db75943
commit 82a9164fb4
2 changed files with 14 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -148,7 +148,8 @@ namespace {
bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
bool SelectScalarSSELoad(SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
SDOperand &Index, SDOperand &Disp,
SDOperand &InChain, SDOperand &OutChain);
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
@ -781,20 +782,22 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand &Base,
SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) {
#if 0
SDOperand &Scale, SDOperand &Index,
SDOperand &Disp, SDOperand &InChain,
SDOperand &OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
if (N.getOperand(0).getOpcode() == ISD::LOAD) {
SDOperand LoadAddr = N.getOperand(0).getOperand(0);
InChain = N.getOperand(0);
if (ISD::isNON_EXTLoad(InChain.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(InChain);
SDOperand LoadAddr = LD->getBasePtr();
if (!SelectAddr(LoadAddr, Base, Scale, Index, Disp))
return false;
OutChain = LD->getChain();
return true;
}
}
// TODO: Also handle the case where we explicitly require zeros in the top
// elements. This is a vector shuffle from the zero vector.
#endif
return false;
}

6
lib/Target/X86/X86InstrSSE.td
View File

@ -39,8 +39,10 @@ def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
// These are 'extloads' from a scalar to the low element of a vector, zeroing
// the top elements. These are used for the SSE 'ss' and 'sd' instruction
// forms.
def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", []>;
def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", []>;
def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
[SDNPHasChain]>;
def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
[SDNPHasChain]>;
def ssmem : Operand<v4f32> {
let PrintMethod = "printf32mem";