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Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3244,6 +3244,8 @@ class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{3-0} = Rm;
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let Unpredictable{11-8} = 0b1111;
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}
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// Saturating add/subtract
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@ -1,12 +0,0 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# Opcode=0 Name=PHI Format=(42)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction.
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0x10 0x51 0x37 0xe6
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7
test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt
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7
test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt
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@ -0,0 +1,7 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# CHECK: warning: potentially undefined
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# CHECK: shadd16 r5, r7, r0
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0x10 0x51 0x37 0xe6
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