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Tests: Use CHECK-LABEL where possible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192403 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -82,7 +82,7 @@ KBBlockZero.exit: ; preds = %bb2.i
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; <rdar://problem/14379453>
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; <rdar://problem/14379453>
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; Hard-coded registers comes from the ABI.
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; Hard-coded registers comes from the ABI.
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; CHECK: wrapDistance:
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; CHECK-LABEL: wrapDistance:
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; CHECK: cmp r1, #59
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; CHECK: cmp r1, #59
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; CHECK-NEXT: itt le
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; CHECK-NEXT: itt le
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; CHECK-NEXT: suble r0, r2, #1
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; CHECK-NEXT: suble r0, r2, #1
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=arm | FileCheck %s
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; RUN: llc < %s -march=arm | FileCheck %s
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define i64 @f0(i64 %A, i64 %B) {
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define i64 @f0(i64 %A, i64 %B) {
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; CHECK: f0
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; CHECK-LABEL: f0:
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; CHECK: lsrs r3, r3, #1
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; CHECK: lsrs r3, r3, #1
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; CHECK-NEXT: rrx r2, r2
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; CHECK-NEXT: rrx r2, r2
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: subs r0, r0, r2
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@ -13,7 +13,7 @@ define i64 @f0(i64 %A, i64 %B) {
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}
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}
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define i32 @f1(i64 %x, i64 %y) {
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define i32 @f1(i64 %x, i64 %y) {
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; CHECK: f1
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; CHECK-LABEL: f1:
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; CHECK: lsl{{.*}}r2
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; CHECK: lsl{{.*}}r2
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%a = shl i64 %x, %y
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%a = shl i64 %x, %y
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%b = trunc i64 %a to i32
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%b = trunc i64 %a to i32
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@ -21,7 +21,7 @@ define i32 @f1(i64 %x, i64 %y) {
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}
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}
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define i32 @f2(i64 %x, i64 %y) {
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define i32 @f2(i64 %x, i64 %y) {
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; CHECK: f2
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; CHECK-LABEL: f2:
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; CHECK: lsr{{.*}}r2
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; CHECK: lsr{{.*}}r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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@ -34,7 +34,7 @@ define i32 @f2(i64 %x, i64 %y) {
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}
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}
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define i32 @f3(i64 %x, i64 %y) {
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define i32 @f3(i64 %x, i64 %y) {
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; CHECK: f3
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; CHECK-LABEL: f3:
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; CHECK: lsr{{.*}}r2
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; CHECK: lsr{{.*}}r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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@ -75,7 +75,7 @@ define double @f7(double %a, double %b) {
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; into the constant pool based on the value of the "icmp". If we have one "it"
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; into the constant pool based on the value of the "icmp". If we have one "it"
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; block generated, odds are good that we have close to the ideal code for this:
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; block generated, odds are good that we have close to the ideal code for this:
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;
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;
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; CHECK-NEON: _f8:
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; CHECK-NEON-LABEL: f8:
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; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
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; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
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; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
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; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
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; CHECK-NEON-NEXT: cmp r0, [[R3]]
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; CHECK-NEON-NEXT: cmp r0, [[R3]]
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@ -113,7 +113,7 @@ entry:
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ret void
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ret void
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}
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}
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; CHECK: f10
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; CHECK-LABEL: f10:
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define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatsisf
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; CHECK-NOT: floatsisf
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%1 = icmp eq i32 %a, %b
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%1 = icmp eq i32 %a, %b
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@ -122,7 +122,7 @@ define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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ret float %3
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ret float %3
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}
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}
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; CHECK: f11
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; CHECK-LABEL: f11:
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define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatsisf
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; CHECK-NOT: floatsisf
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%1 = icmp eq i32 %a, %b
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%1 = icmp eq i32 %a, %b
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@ -130,7 +130,7 @@ define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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ret float %2
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ret float %2
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}
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}
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; CHECK: f12
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; CHECK-LABEL: f12:
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define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatunsisf
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; CHECK-NOT: floatunsisf
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%1 = icmp eq i32 %a, %b
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%1 = icmp eq i32 %a, %b
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@ -29,7 +29,7 @@ entry:
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; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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; converted back to be used as a vector type.
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; converted back to be used as a vector type.
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; CHECK: test_vmovrrd_combine
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; CHECK-LABEL: test_vmovrrd_combine:
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define <4 x i32> @test_vmovrrd_combine() nounwind {
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define <4 x i32> @test_vmovrrd_combine() nounwind {
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entry:
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entry:
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br i1 undef, label %bb1, label %bb2
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br i1 undef, label %bb1, label %bb2
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@ -136,7 +136,7 @@ define i16 @foldBuildVectors() {
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; Test that we are generating vrev and vext for reverse shuffles of v8i16
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; Test that we are generating vrev and vext for reverse shuffles of v8i16
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; shuffles.
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; shuffles.
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; CHECK: reverse_v8i16
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; CHECK-LABEL: reverse_v8i16:
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define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
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define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
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%v0 = load <8 x i16>* %loadaddr
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%v0 = load <8 x i16>* %loadaddr
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; CHECK: vrev64.16
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; CHECK: vrev64.16
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@ -149,7 +149,7 @@ define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
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; Test that we are generating vrev and vext for reverse shuffles of v16i8
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; Test that we are generating vrev and vext for reverse shuffles of v16i8
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; shuffles.
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; shuffles.
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; CHECK: reverse_v16i8
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; CHECK-LABEL: reverse_v16i8:
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define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
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define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
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%v0 = load <16 x i8>* %loadaddr
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%v0 = load <16 x i8>* %loadaddr
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; CHECK: vrev64.8
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; CHECK: vrev64.8
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@ -165,7 +165,7 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
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; vldr cannot handle unaligned loads.
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; vldr cannot handle unaligned loads.
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; Fall back to vld1.32, which can, instead of using the general purpose loads
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; Fall back to vld1.32, which can, instead of using the general purpose loads
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; followed by a costly sequence of instructions to build the vector register.
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; followed by a costly sequence of instructions to build the vector register.
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; CHECK: t3
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; CHECK-LABEL: t3:
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}
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; CHECK: vld1.32 {[[REG]][1]}
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; CHECK: vld1.32 {[[REG]][1]}
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; CHECK: vmull.u8 q{{[0-9]+}}, [[REG]], [[REG]]
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; CHECK: vmull.u8 q{{[0-9]+}}, [[REG]], [[REG]]
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@ -188,7 +188,7 @@ declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>)
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; Check that (insert_vector_elt (load)) => (vector_load).
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; Check that (insert_vector_elt (load)) => (vector_load).
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; Thus, check that scalar_to_vector do not interfer with that.
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; Thus, check that scalar_to_vector do not interfer with that.
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define <8 x i16> @t4(i8* nocapture %sp0) {
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define <8 x i16> @t4(i8* nocapture %sp0) {
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; CHECK: t4
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; CHECK-LABEL: t4:
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; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
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; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
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entry:
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entry:
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%pix_sp0.0.cast = bitcast i8* %sp0 to i32*
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%pix_sp0.0.cast = bitcast i8* %sp0 to i32*
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@ -202,7 +202,7 @@ entry:
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; Make sure vector load is used for all three loads.
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; Make sure vector load is used for all three loads.
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; Lowering to build vector was breaking the single use property of the load of
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; Lowering to build vector was breaking the single use property of the load of
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; %pix_sp0.0.copyload.
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; %pix_sp0.0.copyload.
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; CHECK: t5
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; CHECK-LABEL: t5:
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; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0]
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; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0]
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; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]]
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; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]]
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; CHECK: vld1.32 {[[REG1]][0]}, [r1]
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; CHECK: vld1.32 {[[REG1]][0]}, [r1]
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