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[Sparc] Add support for decoding call instructions in the sparc disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202577 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -190,6 +190,8 @@ static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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#include "SparcGenDisassemblerTables.inc"
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@ -336,3 +338,22 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeQFPRegsRegisterClass);
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
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Offset, Width);
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}
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static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = fieldFromInstruction(insn, 0, 30);
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tgt <<= 2;
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if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
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0, 30, MI, Decoder))
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MI.addOperand(MCOperand::CreateImm(tgt));
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return MCDisassembler::Success;
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}
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@ -106,6 +106,7 @@ def brtarget : Operand<OtherVT> {
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def calltarget : Operand<i32> {
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let EncoderMethod = "getCallTargetOpValue";
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let DecoderMethod = "DecodeCall";
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}
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// Operand for printing out a condition code.
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@ -577,8 +578,8 @@ let Uses = [FCC] in
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// This is the only Format 1 instruction
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let Uses = [O6],
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hasDelaySlot = 1, isCall = 1 in {
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def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
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"call $dst", []> {
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def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
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"call $disp", []> {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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@ -170,3 +170,6 @@
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# CHECK: restore
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0x81 0xe8 0x00 0x00
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# CHECK: call 16
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0x40 0x00 0x00 0x04
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