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Update PowerPC target information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@217304 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -217,6 +217,37 @@ We had also decided that the name of the combined backend should be AArch64,
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following ARM's official documentation. So, at the end of May the old
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AArch64 directory was removed, and ARM64 renamed into its place.
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Changes to the PowerPC Target
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-----------------------------
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The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
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now fully supported. This includes support for the Altivec instruction set.
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The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
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is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI
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for Big Endian. Currently, it is not possible to override these defaults.
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That capability will be available (albeit not recommended) in a future release.
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Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
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specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
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Efforts are underway to move this to a location that doesn't require
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registration, but the planned site isn't ready yet.
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Experimental support for the VSX instruction set introduced with ISA 2.06
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is now available using the ``-mvsx`` switch. Work remains on this, so it
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is not recommended for production use. VSX is disabled for Little Endian
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regardless of this switch setting.
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Load/store cost estimates have been improved.
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Constant hoisting has been enabled.
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Global named register support has been enabled.
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Initial support for PIC code has been added for the 32-bit ELF subtarget.
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Further support will be available in a future release.
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Changes to CMake build system
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-----------------------------
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