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Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov 2014-06-10 12:47:23 +00:00
parent 2093e88d67
commit 8316a97e02
1 changed files with 6 additions and 11 deletions
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17
utils/TableGen/AsmWriterEmitter.cpp
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@ -832,6 +832,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
unsigned MIOpNum = 0; unsigned MIOpNum = 0;
for (unsigned i = 0, e = LastOpNo; i != e; ++i) { for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
switch (RO.Kind) { switch (RO.Kind) {
@ -858,9 +860,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
if (Rec->isSubClassOf("RegisterOperand")) if (Rec->isSubClassOf("RegisterOperand"))
Rec = Rec->getValueAsDef("RegClass"); Rec = Rec->getValueAsDef("RegClass");
if (Rec->isSubClassOf("RegisterClass")) { if (Rec->isSubClassOf("RegisterClass")) {
Cond = std::string("MI->getOperand(") + llvm::utostr(MIOpNum) + IAP->addCond(Op + ".isReg()");
").isReg()";
IAP->addCond(Cond);
if (!IAP->isOpMapped(ROName)) { if (!IAP->isOpMapped(ROName)) {
IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
@ -869,12 +869,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
R = R->getValueAsDef("RegClass"); R = R->getValueAsDef("RegClass");
Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
R->getName() + "RegClassID)" R->getName() + "RegClassID)"
".contains(MI->getOperand(" + ".contains(" + Op + ".getReg())";
llvm::utostr(MIOpNum) + ").getReg())";
IAP->addCond(Cond); IAP->addCond(Cond);
} else { } else {
Cond = std::string("MI->getOperand(") + Cond = Op + ".getReg() == MI->getOperand(" +
llvm::utostr(MIOpNum) + ").getReg() == MI->getOperand(" +
llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
IAP->addCond(Cond); IAP->addCond(Cond);
} }
@ -887,8 +885,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
break; break;
} }
case CodeGenInstAlias::ResultOperand::K_Imm: { case CodeGenInstAlias::ResultOperand::K_Imm: {
std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
// Just because the alias has an immediate result, doesn't mean the // Just because the alias has an immediate result, doesn't mean the
// MCInst will. An MCExpr could be present, for example. // MCInst will. An MCExpr could be present, for example.
IAP->addCond(Op + ".isImm()"); IAP->addCond(Op + ".isImm()");
@ -906,8 +902,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
break; break;
} }
Cond = std::string("MI->getOperand(") + Cond = Op + ".getReg() == " + Target.getName() +
llvm::utostr(MIOpNum) + ").getReg() == " + Target.getName() +
"::" + CGA->ResultOperands[i].getRegister()->getName(); "::" + CGA->ResultOperands[i].getRegister()->getName();
IAP->addCond(Cond); IAP->addCond(Cond);
break; break;