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Switch over to tablegen generated header files

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-08-03 15:48:55 +00:00
parent 7ad3e063f5
commit 832003578e
1 changed files with 6 additions and 9 deletions
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15
lib/Target/X86/X86.h
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@ -13,7 +13,7 @@ class TargetMachine;
class Pass;
/// createX86SimpleInstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
/// into a machine code representation in a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple.
///
Pass *createX86SimpleInstructionSelector(TargetMachine &TM);
@ -42,18 +42,15 @@ Pass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm);
///
Pass *createEmitX86CodeToMemory();
// Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number.
//
#include "X86GenRegisterNames.inc"
/// X86 namespace - This namespace contains all of the register and opcode enums
/// used by the X86 backend.
///
namespace X86 {
// Defines a large number of symbolic names for X86 registers. This defines a
// mapping from register name to register number.
//
enum Register {
#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) ENUM,
#include "X86RegisterInfo.def"
};
// This defines a large number of symbolic names for X86 instruction opcodes.
enum Opcode {
#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,