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More encoding cleanup. Also add register Rd operands for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1076,6 +1076,7 @@ let isCall = 1,
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsARM, IsNotDarwin]> {
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let Inst{31-28} = 0b1110;
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// FIXME: Encoding info for $func. Needs fixups bits.
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}
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def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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@ -1089,9 +1090,7 @@ let isCall = 1,
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[(ARMcall GPR:$func)]>,
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Requires<[IsARM, HasV5T, IsNotDarwin]> {
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bits<4> func;
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let Inst{7-4} = 0b0011;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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let Inst{27-4} = 0b000100101111111111110011;
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let Inst{3-0} = func;
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}
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@ -1101,9 +1100,9 @@ let isCall = 1,
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IIC_Br, "mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, HasV4T, IsNotDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110001;
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let Inst{3-0} = func;
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}
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// ARMv4
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@ -1111,10 +1110,9 @@ let isCall = 1,
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IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, NoV4T, IsNotDarwin]> {
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let Inst{11-4} = 0b00000000;
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let Inst{15-12} = 0b1111;
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let Inst{19-16} = 0b0000;
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let Inst{27-20} = 0b00011010;
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bits<4> func;
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let Inst{27-4} = 0b000110100000111100000000;
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let Inst{3-0} = func;
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}
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}
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@ -1128,6 +1126,7 @@ let isCall = 1,
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IIC_Br, "bl\t$func",
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[(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
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let Inst{31-28} = 0b1110;
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// FIXME: Encoding info for $func. Needs fixups bits.
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}
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def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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@ -1139,9 +1138,9 @@ let isCall = 1,
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def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
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IIC_Br, "blx\t$func",
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[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
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let Inst{7-4} = 0b0011;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110011;
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let Inst{3-0} = func;
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}
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// ARMv4T
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@ -1150,9 +1149,9 @@ let isCall = 1,
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IIC_Br, "mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, HasV4T, IsDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110001;
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let Inst{3-0} = func;
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}
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// ARMv4
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@ -1160,15 +1159,16 @@ let isCall = 1,
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IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, NoV4T, IsDarwin]> {
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let Inst{11-4} = 0b00000000;
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let Inst{15-12} = 0b1111;
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let Inst{19-16} = 0b0000;
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let Inst{27-20} = 0b00011010;
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bits<4> func;
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let Inst{27-4} = 0b000110100000111100000000;
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let Inst{3-0} = func;
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}
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}
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// Tail calls.
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// FIXME: These should probably be xformed into the non-TC versions of the
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// instructions as part of MC lowering.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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// Darwin versions.
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let Defs = [R0, R1, R2, R3, R9, R12,
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