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Implement support for x86 fastisel of small fixed-sized memcpys, which are generated
en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x and shrinks the generated .s file by 5% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129755 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -486,8 +486,7 @@ bool FastISel::SelectCall(const User *I) {
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if (!F) return false;
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// Handle selected intrinsic function calls.
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unsigned IID = F->getIntrinsicID();
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switch (IID) {
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switch (F->getIntrinsicID()) {
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default: break;
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case Intrinsic::dbg_declare: {
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const DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
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@ -552,64 +551,57 @@ bool FastISel::SelectCall(const User *I) {
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}
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case Intrinsic::eh_exception: {
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EVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
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default: break;
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case TargetLowering::Expand: {
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assert(FuncInfo.MBB->isLandingPad() &&
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"Call to eh.exception not in landing pad!");
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unsigned Reg = TLI.getExceptionAddressRegister();
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(Reg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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break;
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if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand)
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break;
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assert(FuncInfo.MBB->isLandingPad() &&
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"Call to eh.exception not in landing pad!");
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unsigned Reg = TLI.getExceptionAddressRegister();
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(Reg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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case Intrinsic::eh_selector: {
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EVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
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default: break;
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case TargetLowering::Expand: {
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if (FuncInfo.MBB->isLandingPad())
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AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
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else {
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if (TLI.getOperationAction(ISD::EHSELECTION, VT) != TargetLowering::Expand)
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break;
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if (FuncInfo.MBB->isLandingPad())
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AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
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else {
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#ifndef NDEBUG
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FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
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FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
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#endif
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// FIXME: Mark exception selector register as live in. Hack for PR1508.
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unsigned Reg = TLI.getExceptionSelectorRegister();
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if (Reg) FuncInfo.MBB->addLiveIn(Reg);
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}
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// FIXME: Mark exception selector register as live in. Hack for PR1508.
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unsigned Reg = TLI.getExceptionSelectorRegister();
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EVT SrcVT = TLI.getPointerTy();
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const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(Reg);
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bool ResultRegIsKill = hasTrivialKill(I);
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// Cast the register to the type of the selector.
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if (SrcVT.bitsGT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
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ResultReg, ResultRegIsKill);
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else if (SrcVT.bitsLT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
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ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
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if (ResultReg == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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UpdateValueMap(I, ResultReg);
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return true;
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if (Reg) FuncInfo.MBB->addLiveIn(Reg);
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}
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}
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break;
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unsigned Reg = TLI.getExceptionSelectorRegister();
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EVT SrcVT = TLI.getPointerTy();
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const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(Reg);
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bool ResultRegIsKill = hasTrivialKill(I);
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// Cast the register to the type of the selector.
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if (SrcVT.bitsGT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
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ResultReg, ResultRegIsKill);
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else if (SrcVT.bitsLT(MVT::i32))
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ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
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ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
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if (ResultReg == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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@ -1325,6 +1325,52 @@ bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
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// FIXME: Handle more intrinsics.
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switch (I.getIntrinsicID()) {
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default: return false;
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case Intrinsic::memcpy: {
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const MemCpyInst &MCI = cast<MemCpyInst>(I);
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// Don't handle volatile or variable length memcpys.
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if (MCI.isVolatile() || !isa<ConstantInt>(MCI.getLength()))
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return false;
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// Don't inline super long memcpys. We could lower these to a memcpy call,
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// but we might as well bail out.
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uint64_t Len = cast<ConstantInt>(MCI.getLength())->getZExtValue();
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bool i64Legal = TLI.isTypeLegal(MVT::i64);
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if (Len > (i64Legal ? 32 : 16)) return false;
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// Get the address of the dest and source addresses.
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X86AddressMode DestAM, SrcAM;
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if (!X86SelectAddress(MCI.getRawDest(), DestAM) ||
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!X86SelectAddress(MCI.getRawSource(), SrcAM))
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return false;
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// We don't care about alignment here since we just emit integer accesses.
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while (Len) {
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MVT VT;
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if (Len >= 8 && i64Legal)
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VT = MVT::i64;
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else if (Len >= 4)
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VT = MVT::i32;
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else if (Len >= 2)
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VT = MVT::i16;
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else {
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assert(Len == 1);
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VT = MVT::i8;
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}
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unsigned Reg;
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bool RV = X86FastEmitLoad(VT, SrcAM, Reg);
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RV &= X86FastEmitStore(VT, Reg, DestAM);
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assert(RV && "Failed to emit load or store??");
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unsigned Size = VT.getSizeInBits()/8;
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Len -= Size;
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DestAM.Disp += Size;
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SrcAM.Disp += Size;
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}
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return true;
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}
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case Intrinsic::stackprotector: {
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// Emit code inline code to store the stack guard onto the stack.
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EVT PtrTy = TLI.getPointerTy();
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@ -1335,17 +1381,14 @@ bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
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// Grab the frame index.
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X86AddressMode AM;
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if (!X86SelectAddress(Slot, AM)) return false;
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if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
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return true;
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}
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case Intrinsic::objectsize: {
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ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
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// FIXME: This should be moved to generic code!
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ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
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const Type *Ty = I.getCalledFunction()->getReturnType();
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assert(CI && "Non-constant type in Intrinsic::objectsize?");
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MVT VT;
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if (!isTypeLegal(Ty, VT))
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return false;
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@ -1383,6 +1426,8 @@ bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
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}
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow: {
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// FIXME: Should fold immediates.
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// Replace "add with overflow" intrinsics with an "add" instruction followed
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// by a seto/setc instruction. Later on, when the "extractvalue"
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// instructions are encountered, we use the fact that two registers were
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@ -170,3 +170,14 @@ entry:
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; CHECK: callq
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
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; rdar://9289488 - fast-isel shouldn't bail out on llvm.memcpy
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define void @test15(i8* %a, i8* %b) nounwind {
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false)
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ret void
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; CHECK: test15:
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; CHECK-NEXT: movl (%rsi), %eax
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; CHECK-NEXT: movl %eax, (%rdi)
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; CHECK-NEXT: ret
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}
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