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R600/SI: Fix extra defs of VCC / SCC.

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When replacing scalar operations with vector,
the wrong implicit output register was used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2013-11-18 20:09:21 +00:00
parent b570599c8f
commit 836c5133c6
1 changed files with 15 additions and 4 deletions
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19
lib/Target/R600/SIInstrInfo.cpp
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@@ -466,6 +466,8 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
continue; // VGPRs are legal continue; // VGPRs are legal
assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) { if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
SGPRReg = MO.getReg(); SGPRReg = MO.getReg();
// We can use one SGPR in each VOP3 instruction. // We can use one SGPR in each VOP3 instruction.
@@ -543,18 +545,27 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
const MCInstrDesc &NewDesc = get(NewOpcode); const MCInstrDesc &NewDesc = get(NewOpcode);
Inst->setDesc(NewDesc); Inst->setDesc(NewDesc);
// Remove any references to SCC. Vector instructions can't read from it, and
// We're just about to add the implicit use / defs of VCC, and we don't want
// both.
for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
MachineOperand &Op = Inst->getOperand(i);
if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
Inst->RemoveOperand(i);
}
// Add the implict and explicit register definitions. // Add the implict and explicit register definitions.
if (NewDesc.ImplicitUses) { if (NewDesc.ImplicitUses) {
for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) { for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitUses[i], unsigned Reg = NewDesc.ImplicitUses[i];
false, true)); Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
} }
} }
if (NewDesc.ImplicitDefs) { if (NewDesc.ImplicitDefs) {
for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) { for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitDefs[i], unsigned Reg = NewDesc.ImplicitDefs[i];
true, true)); Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
} }
} }