mirror of
https://github.com/c64scene-ar/llvm-6502.git
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More DebugLoc propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63454 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
c144a57e14
commit
836ca7dc6e
@ -202,10 +202,10 @@ namespace {
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bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
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SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
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SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2);
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SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2,
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SDValue N3, ISD::CondCode CC,
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bool NotExtCompare = false);
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SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
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SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
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SDValue N3, ISD::CondCode CC,
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bool NotExtCompare = false);
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SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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bool foldBooleans = true);
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SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
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@ -229,13 +229,13 @@ namespace {
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bool isAlias(SDValue Ptr1, int64_t Size1,
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const Value *SrcValue1, int SrcValueOffset1,
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SDValue Ptr2, int64_t Size2,
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const Value *SrcValue2, int SrcValueOffset2);
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const Value *SrcValue2, int SrcValueOffset2) const;
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/// FindAliasInfo - Extracts the relevant alias information from the memory
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/// node. Returns true if the operand was a load.
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bool FindAliasInfo(SDNode *N,
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SDValue &Ptr, int64_t &Size,
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const Value *&SrcValue, int &SrcValueOffset);
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const Value *&SrcValue, int &SrcValueOffset) const;
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/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
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/// looking for a better chain (aliasing node.)
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@ -2882,7 +2882,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
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N0.getOperand(0), N0.getOperand(1),
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N1, N2, N0.getOperand(2));
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else
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return SimplifySelect(N0, N1, N2);
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return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
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}
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return SDValue();
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@ -2923,7 +2923,7 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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return SDValue(N, 0); // Don't revisit N.
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// fold select_cc into other things, such as min/max/abs
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return SimplifySelectCC(N0, N1, N2, N3, CC);
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return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
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}
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SDValue DAGCombiner::visitSETCC(SDNode *N) {
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@ -3131,7 +3131,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
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if (N0.getOpcode() == ISD::SETCC) {
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SDValue SCC =
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SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
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SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
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DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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if (SCC.getNode()) return SCC;
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@ -3266,7 +3266,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
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if (N0.getOpcode() == ISD::SETCC) {
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SDValue SCC =
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SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
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SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
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DAG.getConstant(1, VT), DAG.getConstant(0, VT),
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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if (SCC.getNode()) return SCC;
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@ -3374,7 +3374,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
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if (N0.getOpcode() == ISD::SETCC) {
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SDValue SCC =
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SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
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SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
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DAG.getConstant(1, VT), DAG.getConstant(0, VT),
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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if (SCC.getNode())
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@ -5460,21 +5460,25 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
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MVT VT = MVT::getVectorVT(EVT, NumElts);
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MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
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std::vector<SDValue> Ops;
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LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
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LHS = DAG.getNode(ISD::BIT_CONVERT, DebugLoc::getUnknownLoc(), VT, LHS);
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Ops.push_back(LHS);
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AddToWorkList(LHS.getNode());
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std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
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&ZeroOps[0], ZeroOps.size()));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&IdxOps[0], IdxOps.size()));
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SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
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&Ops[0], Ops.size());
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
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VT, &ZeroOps[0], ZeroOps.size()));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
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MaskVT, &IdxOps[0], IdxOps.size()));
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SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
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VT, &Ops[0], Ops.size());
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if (VT != N->getValueType(0))
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Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result);
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Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
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N->getValueType(0), Result);
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return Result;
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}
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}
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return SDValue();
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}
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@ -5510,6 +5514,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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RHSOp.getOpcode() != ISD::Constant &&
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RHSOp.getOpcode() != ISD::ConstantFP))
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break;
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// Can't fold divide by zero.
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if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
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N->getOpcode() == ISD::FDIV) {
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@ -5519,7 +5524,9 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
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break;
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}
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Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
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Ops.push_back(DAG.getNode(N->getOpcode(), DebugLoc::getUnknownLoc(),
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EltType, LHSOp, RHSOp));
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AddToWorkList(Ops.back().getNode());
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assert((Ops.back().getOpcode() == ISD::UNDEF ||
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Ops.back().getOpcode() == ISD::Constant ||
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@ -5529,18 +5536,21 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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if (Ops.size() == LHS.getNumOperands()) {
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MVT VT = LHS.getValueType();
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return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
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return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
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&Ops[0], Ops.size());
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}
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}
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return SDValue();
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}
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SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
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SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
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SDValue N1, SDValue N2){
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assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
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SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
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SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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// If we got a simplified select_cc node back from SimplifySelectCC, then
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// break it down into a new SETCC node, and a new SELECT node, and then return
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// the SELECT node, since we were called with a SELECT node.
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@ -5548,13 +5558,15 @@ SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
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// Check to see if we got a select_cc back (to turn into setcc/select).
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// Otherwise, just return whatever node we got back, like fabs.
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if (SCC.getOpcode() == ISD::SELECT_CC) {
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SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
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SCC.getOperand(0), SCC.getOperand(1),
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SCC.getOperand(4));
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SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
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N0.getValueType(),
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SCC.getOperand(0), SCC.getOperand(1),
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SCC.getOperand(4));
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AddToWorkList(SETCC.getNode());
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return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
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SCC.getOperand(3), SETCC);
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return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
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SCC.getOperand(2), SCC.getOperand(3), SETCC);
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}
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return SCC;
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}
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return SDValue();
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@ -5566,7 +5578,6 @@ SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
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/// returns true. As such, they should return the appropriate thing (e.g. the
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/// node) back to the top-level of the DAG combiner loop to avoid it being
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/// looked at.
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///
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bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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SDValue RHS) {
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@ -5597,7 +5608,8 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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// this will induce a cycle into the DAG.
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if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
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Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
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Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0), LLD->getBasePtr(),
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RLD->getBasePtr());
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}
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@ -5608,24 +5620,28 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
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!RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
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Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0),
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TheSelect->getOperand(1),
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LLD->getBasePtr(), RLD->getBasePtr(),
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TheSelect->getOperand(4));
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Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0),
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TheSelect->getOperand(1),
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LLD->getBasePtr(), RLD->getBasePtr(),
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TheSelect->getOperand(4));
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}
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}
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if (Addr.getNode()) {
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SDValue Load;
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if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
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Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
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if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
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Load = DAG.getLoad(TheSelect->getValueType(0),
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TheSelect->getDebugLoc(),
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LLD->getChain(),
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Addr,LLD->getSrcValue(),
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LLD->getSrcValueOffset(),
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LLD->isVolatile(),
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LLD->getAlignment());
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else {
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} else {
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Load = DAG.getExtLoad(LLD->getExtensionType(),
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TheSelect->getDebugLoc(),
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TheSelect->getValueType(0),
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LLD->getChain(), Addr, LLD->getSrcValue(),
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LLD->getSrcValueOffset(),
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@ -5633,6 +5649,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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LLD->isVolatile(),
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LLD->getAlignment());
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}
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// Users of the select now use the result of the load.
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CombineTo(TheSelect, Load);
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@ -5649,10 +5666,9 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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return false;
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}
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SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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SDValue N2, SDValue N3,
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ISD::CondCode CC, bool NotExtCompare) {
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MVT VT = N2.getValueType();
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
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@ -5679,18 +5695,18 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
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N0 == N2 && N3.getOpcode() == ISD::FNEG &&
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N2 == N3.getOperand(0))
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return DAG.getNode(ISD::FABS, VT, N0);
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return DAG.getNode(ISD::FABS, DL, VT, N0);
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// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
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if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
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N0 == N3 && N2.getOpcode() == ISD::FNEG &&
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N2.getOperand(0) == N3)
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return DAG.getNode(ISD::FABS, VT, N3);
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return DAG.getNode(ISD::FABS, DL, VT, N3);
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}
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}
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// Check to see if we can perform the "gzip trick", transforming
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// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
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// (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
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if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
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N0.getValueType().isInteger() &&
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N2.getValueType().isInteger() &&
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@ -5705,23 +5721,32 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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unsigned ShCtV = N2C->getAPIntValue().logBase2();
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ShCtV = XType.getSizeInBits()-ShCtV-1;
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SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
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SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
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SDValue Shift = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(),
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XType, N0, ShCt);
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AddToWorkList(Shift.getNode());
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if (XType.bitsGT(AType)) {
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Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
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Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(),
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AType, Shift);
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AddToWorkList(Shift.getNode());
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}
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return DAG.getNode(ISD::AND, AType, Shift, N2);
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return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
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}
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SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
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DAG.getConstant(XType.getSizeInBits()-1,
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TLI.getShiftAmountTy()));
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SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(),
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XType, N0,
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DAG.getConstant(XType.getSizeInBits()-1,
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TLI.getShiftAmountTy()));
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AddToWorkList(Shift.getNode());
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if (XType.bitsGT(AType)) {
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Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
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Shift = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(),
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AType, Shift);
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AddToWorkList(Shift.getNode());
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}
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return DAG.getNode(ISD::AND, AType, Shift, N2);
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return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
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}
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}
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@ -5740,23 +5765,29 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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SDValue Temp, SCC;
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// cast from setcc result type to select result type
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if (LegalTypes) {
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SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()),
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SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(),
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TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC);
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if (N2.getValueType().bitsLT(SCC.getValueType()))
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Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
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Temp = DAG.getZeroExtendInReg(SCC, DebugLoc::getUnknownLoc(),
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N2.getValueType());
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else
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Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
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Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(),
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N2.getValueType(), SCC);
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} else {
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SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
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Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
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SCC = DAG.getSetCC(DebugLoc::getUnknownLoc(), MVT::i1, N0, N1, CC);
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Temp = DAG.getNode(ISD::ZERO_EXTEND, DebugLoc::getUnknownLoc(),
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N2.getValueType(), SCC);
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}
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AddToWorkList(SCC.getNode());
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AddToWorkList(Temp.getNode());
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if (N2C->getAPIntValue() == 1)
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return Temp;
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// shl setcc result by log2 n2c
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return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
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return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
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DAG.getConstant(N2C->getAPIntValue().logBase2(),
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TLI.getShiftAmountTy()));
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}
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@ -5768,37 +5799,38 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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MVT XType = N0.getValueType();
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if (!LegalOperations ||
|
||||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
|
||||
SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC);
|
||||
SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
|
||||
if (Res.getValueType() != VT)
|
||||
Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
|
||||
Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
|
||||
return Res;
|
||||
}
|
||||
|
||||
// seteq X, 0 -> srl (ctlz X, log2(size(X)))
|
||||
// fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
|
||||
if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
|
||||
(!LegalOperations ||
|
||||
TLI.isOperationLegal(ISD::CTLZ, XType))) {
|
||||
SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
|
||||
return DAG.getNode(ISD::SRL, XType, Ctlz,
|
||||
SDValue Ctlz = DAG.getNode(ISD::CTLZ, DebugLoc::getUnknownLoc(),
|
||||
XType, N0);
|
||||
return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
|
||||
DAG.getConstant(Log2_32(XType.getSizeInBits()),
|
||||
TLI.getShiftAmountTy()));
|
||||
}
|
||||
// setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
|
||||
// fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
|
||||
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
|
||||
SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
|
||||
N0);
|
||||
SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
|
||||
XType, DAG.getConstant(0, XType), N0);
|
||||
SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
|
||||
return DAG.getNode(ISD::SRL, XType,
|
||||
return DAG.getNode(ISD::SRL, DL, XType,
|
||||
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
}
|
||||
// setgt X, -1 -> xor (srl (X, size(X)-1), 1)
|
||||
// fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
|
||||
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
|
||||
SDValue Sign = DAG.getNode(ISD::SRL, XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
|
||||
SDValue Sign = DAG.getNode(ISD::SRL, DebugLoc::getUnknownLoc(), XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
|
||||
}
|
||||
}
|
||||
|
||||
@ -5808,13 +5840,14 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
|
||||
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
|
||||
N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
|
||||
MVT XType = N0.getValueType();
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), XType,
|
||||
N0, Shift);
|
||||
AddToWorkList(Shift.getNode());
|
||||
AddToWorkList(Add.getNode());
|
||||
return DAG.getNode(ISD::XOR, XType, Add, Shift);
|
||||
return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
|
||||
}
|
||||
// Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
|
||||
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
|
||||
@ -5823,13 +5856,15 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
|
||||
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
|
||||
MVT XType = N0.getValueType();
|
||||
if (SubC->isNullValue() && XType.isInteger()) {
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
|
||||
SDValue Shift = DAG.getNode(ISD::SRA, DebugLoc::getUnknownLoc(), XType,
|
||||
N0,
|
||||
DAG.getConstant(XType.getSizeInBits()-1,
|
||||
TLI.getShiftAmountTy()));
|
||||
SDValue Add = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(),
|
||||
XType, N0, Shift);
|
||||
AddToWorkList(Shift.getNode());
|
||||
AddToWorkList(Add.getNode());
|
||||
return DAG.getNode(ISD::XOR, XType, Add, Shift);
|
||||
return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -5899,8 +5934,7 @@ static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
|
||||
bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
|
||||
const Value *SrcValue1, int SrcValueOffset1,
|
||||
SDValue Ptr2, int64_t Size2,
|
||||
const Value *SrcValue2, int SrcValueOffset2)
|
||||
{
|
||||
const Value *SrcValue2, int SrcValueOffset2) const {
|
||||
// If they are the same then they must be aliases.
|
||||
if (Ptr1 == Ptr2) return true;
|
||||
|
||||
@ -5911,10 +5945,9 @@ bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
|
||||
bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
|
||||
|
||||
// If they have a same base address then...
|
||||
if (Base1 == Base2) {
|
||||
if (Base1 == Base2)
|
||||
// Check to see if the addresses overlap.
|
||||
return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
|
||||
}
|
||||
return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
|
||||
|
||||
// If we know both bases then they can't alias.
|
||||
if (KnownBase1 && KnownBase2) return false;
|
||||
@ -5938,7 +5971,7 @@ bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
|
||||
/// node. Returns true if the operand was a load.
|
||||
bool DAGCombiner::FindAliasInfo(SDNode *N,
|
||||
SDValue &Ptr, int64_t &Size,
|
||||
const Value *&SrcValue, int &SrcValueOffset) {
|
||||
const Value *&SrcValue, int &SrcValueOffset) const {
|
||||
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
|
||||
Ptr = LD->getBasePtr();
|
||||
Size = LD->getMemoryVT().getSizeInBits() >> 3;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user