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Enable sub-sub-register copy coalescing.
It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156878 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -278,15 +278,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
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SrcIdx, DstIdx);
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SrcIdx, DstIdx);
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if (!NewRC)
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if (!NewRC)
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return false;
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return false;
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// We cannot handle the case where both Src and Dst would be a
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// sub-register. Yet.
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if (SrcIdx && DstIdx) {
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DEBUG(dbgs() << "\tCannot handle " << NewRC->getName()
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<< " with subregs " << TRI.getSubRegIndexName(SrcIdx)
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<< " and " << TRI.getSubRegIndexName(DstIdx) << '\n');
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return false;
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}
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} else if (DstSub) {
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} else if (DstSub) {
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// SrcReg will be merged with a sub-register of DstReg.
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// SrcReg will be merged with a sub-register of DstReg.
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SrcIdx = DstSub;
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SrcIdx = DstSub;
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68
test/CodeGen/ARM/coalesce-subregs.ll
Normal file
68
test/CodeGen/ARM/coalesce-subregs.ll
Normal file
@ -0,0 +1,68 @@
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; RUN: llc < %s -mcpu=cortex-a9 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios0.0.0"
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; CHECK: f
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; The vld2 and vst2 are not aligned wrt each other, the second Q loaded is the
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; first one stored.
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; The coalescer must find a super-register larger than QQ to eliminate the copy
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; setting up the vst2 data.
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; CHECK: vld2
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; CHECK-NOT: vorr
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; CHECK-NOT: vmov
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; CHECK: vst2
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define void @f(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
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ret void
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}
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; CHECK: f1
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; FIXME: This function still has copies.
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define void @f1(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
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ret void
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}
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; CHECK: f2
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; FIXME: This function still has copies.
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define void @f2(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
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%c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
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%p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
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%add.ptr = getelementptr inbounds float* %p.addr.0, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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%vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
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%dec = add nsw i32 %c.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end: ; preds = %do.body
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ret void
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}
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declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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