mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Encode pic load / store instructions; fix some encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
ec740e325c
commit
83b5cf0272
@ -65,8 +65,12 @@ namespace {
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private:
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void emitWordLE(unsigned Binary);
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void emitConstPoolInstruction(const MachineInstr &MI);
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void addPCLabel(unsigned LabelID);
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void emitPseudoInstruction(const MachineInstr &MI);
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unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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@ -81,11 +85,14 @@ namespace {
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unsigned getAddrModeSBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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void emitDataProcessingInstruction(const MachineInstr &MI);
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void emitDataProcessingInstruction(const MachineInstr &MI,
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unsigned ImplicitRn = 0);
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void emitLoadStoreInstruction(const MachineInstr &MI);
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void emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn = 0);
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void emitMiscLoadStoreInstruction(const MachineInstr &MI);
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void emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn = 0);
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void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
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@ -114,9 +121,9 @@ namespace {
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return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
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///
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unsigned getShiftOp(const MachineOperand &MO) const ;
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unsigned getShiftOp(unsigned Imm) const ;
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/// Routines that handle operands which add machine relocations which are
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/// fixed up by the JIT fixup stage.
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@ -165,10 +172,10 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
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///
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unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
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switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
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unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
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switch (ARM_AM::getAM2ShiftOpc(Imm)) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr: return 2;
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case ARM_AM::lsl: return 0;
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@ -246,6 +253,11 @@ void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
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ARM::reloc_arm_branch, BB));
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}
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void ARMCodeEmitter::emitWordLE(unsigned Binary) {
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DOUT << "\t" << (void*)Binary << "\n";
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MCE.emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
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@ -312,7 +324,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
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emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
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}
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MCE.emitWordLE(0);
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emitWordLE(0);
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} else {
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Constant *CV = MCPE.Val.ConstVal;
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@ -321,17 +333,23 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
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if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
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emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
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MCE.emitWordLE(0);
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emitWordLE(0);
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} else {
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assert(CV->getType()->isInteger() &&
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"Not expecting non-integer constpool entries yet!");
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const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
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uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
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MCE.emitWordLE(Val);
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emitWordLE(Val);
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}
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}
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}
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void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
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DOUT << "\t** LPC" << LabelID << " @ "
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<< (void*)MCE.getCurrentPCValue() << '\n';
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JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
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}
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void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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unsigned Opcode = MI.getDesc().Opcode;
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switch (Opcode) {
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@ -342,13 +360,29 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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break;
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case ARM::PICADD: {
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// Remember of the address of the PC label for relocation later.
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const MachineOperand &MO2 = MI.getOperand(2);
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DOUT << "\t** LPC" << MO2.getImm() << " @ "
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<< (void*)MCE.getCurrentPCValue() << '\n';
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JTI->addPCLabelAddr(MO2.getImm(), MCE.getCurrentPCValue());
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addPCLabel(MI.getOperand(2).getImm());
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// PICADD is just an add instruction that implicitly read pc.
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emitDataProcessingInstruction(MI);
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emitDataProcessingInstruction(MI, ARM::PC);
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break;
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}
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case ARM::PICLDR:
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case ARM::PICLDRB:
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case ARM::PICSTR:
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case ARM::PICSTRB: {
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// Remember of the address of the PC label for relocation later.
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addPCLabel(MI.getOperand(2).getImm());
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// These are just load / store instructions that implicitly read pc.
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emitLoadStoreInstruction(MI, ARM::PC);
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break;
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}
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case ARM::PICLDRH:
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case ARM::PICLDRSH:
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case ARM::PICLDRSB:
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case ARM::PICSTRH: {
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// Remember of the address of the PC label for relocation later.
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addPCLabel(MI.getOperand(2).getImm());
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// These are just load / store instructions that implicitly read pc.
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emitMiscLoadStoreInstruction(MI, ARM::PC);
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break;
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}
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}
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@ -434,7 +468,8 @@ unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
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return 0;
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}
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void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI) {
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void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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if (TID.getOpcode() == ARM::MOVi2pieces)
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abort(); // FIXME
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@ -459,9 +494,9 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI) {
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// Encode first non-shifter register operand if there is one.
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bool isUnary = TID.TSFlags & ARMII::UnaryDP;
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if (!isUnary) {
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if (TID.getOpcode() == ARM::PICADD)
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// Special handling for PICADD. It implicitly uses PC register.
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ARM::PC)
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if (ImplicitRn)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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<< ARMII::RegRnShift);
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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@ -473,13 +508,13 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI) {
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const MachineOperand &MO = MI.getOperand(OpIdx);
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if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
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// Encode SoReg.
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MCE.emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
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emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
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return;
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}
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if (MO.isReg()) {
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// Encode register Rm.
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MCE.emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
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emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
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return;
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}
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@ -488,10 +523,11 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI) {
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Binary |= 1 << ARMII::I_BitShift;
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Binary |= getMachineSoImmOpValue(MI, TID, MO);
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI) {
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void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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@ -504,19 +540,28 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI) {
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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// Set second operand
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Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
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unsigned OpIdx = 1;
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if (ImplicitRn)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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<< ARMII::RegRnShift);
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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const MachineOperand &MO2 = MI.getOperand(2);
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const MachineOperand &MO3 = MI.getOperand(3);
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM2Opc = (OpIdx == TID.getNumOperands())
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? 0 : MI.getOperand(OpIdx+1).getImm();
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// Set bit U(23) according to sign of immed value (positive or negative).
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Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
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Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
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ARMII::U_BitShift);
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if (!MO2.getReg()) { // is immediate
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if (ARM_AM::getAM2Offset(MO3.getImm()))
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if (ARM_AM::getAM2Offset(AM2Opc))
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// Set the value of offset_12 field
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Binary |= ARM_AM::getAM2Offset(MO3.getImm());
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MCE.emitWordLE(Binary);
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Binary |= ARM_AM::getAM2Offset(AM2Opc);
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emitWordLE(Binary);
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return;
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}
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@ -528,15 +573,16 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI) {
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// if this instr is in scaled register offset/index instruction, set
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// shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
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Binary |= getShiftOp(MO3) << 5; // shift
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Binary |= ShImm << 7; // shift_immed
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if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
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Binary |= getShiftOp(AM2Opc) << 5; // shift
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Binary |= ShImm << 7; // shift_immed
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}
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI) {
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void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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@ -549,37 +595,44 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI) {
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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// Set second operand
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Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
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unsigned OpIdx = 1;
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if (ImplicitRn)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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<< ARMII::RegRnShift);
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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const MachineOperand &MO2 = MI.getOperand(2);
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const MachineOperand &MO3 = MI.getOperand(3);
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM3Opc = (OpIdx == TID.getNumOperands())
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? 0 : MI.getOperand(OpIdx+1).getImm();
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// Set bit U(23) according to sign of immed value (positive or negative)
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Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
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Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
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ARMII::U_BitShift);
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// If this instr is in register offset/index encoding, set bit[3:0]
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// to the corresponding Rm register.
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if (MO2.getReg()) {
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Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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return;
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}
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// if this instr is in immediate offset/index encoding, set bit 22 to 1
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
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Binary |= 1 << 22;
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// Set operands
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Binary |= (ImmOffs >> 4) << 8; // immedH
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Binary |= (ImmOffs & ~0xF); // immedL
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}
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -619,7 +672,7 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
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Binary |= 0x1 << RegNum;
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}
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitMulFrm1Instruction(const MachineInstr &MI) {
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@ -649,7 +702,7 @@ void ARMCodeEmitter::emitMulFrm1Instruction(const MachineInstr &MI) {
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// Encode Rs
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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@ -670,7 +723,7 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
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}
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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@ -691,7 +744,7 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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// otherwise, set the return register
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Binary |= getMachineOpValue(MI, 0);
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MCE.emitWordLE(Binary);
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emitWordLE(Binary);
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}
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#include "ARMGenCodeEmitter.inc"
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@ -235,81 +235,89 @@ class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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asm, "", pattern> {
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let Inst{27-26} = {0,1};
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}
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class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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// loads
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class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
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"", pattern> {
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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// stores
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class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{20} = 0; // L bit
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, list<dag> pattern>
|
||||
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
|
||||
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
|
||||
asm, "", pattern> {
|
||||
let Inst{20} = 0; // L bit
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{20} = 0; // L bit
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
|
||||
// Pre-indexed loads
|
||||
@ -321,6 +329,7 @@ class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 1; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
@ -330,6 +339,7 @@ class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 1; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
|
||||
// Pre-indexed stores
|
||||
@ -341,6 +351,7 @@ class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 1; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
@ -350,6 +361,7 @@ class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 1; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 1; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
|
||||
// Post-indexed loads
|
||||
@ -361,6 +373,7 @@ class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 0; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
@ -370,6 +383,7 @@ class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 0; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
|
||||
// Post-indexed stores
|
||||
@ -381,6 +395,7 @@ class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 0; // B bit
|
||||
let Inst{24} = 0; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
@ -390,6 +405,7 @@ class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
let Inst{21} = 0; // W bit
|
||||
let Inst{22} = 1; // B bit
|
||||
let Inst{24} = 0; // P bit
|
||||
let Inst{27-26} = {0,1};
|
||||
}
|
||||
|
||||
// addrmode3 instructions
|
||||
@ -417,8 +433,8 @@ class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
}
|
||||
class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{5} = 1; // H bit
|
||||
let Inst{6} = 0; // S bit
|
||||
@ -441,8 +457,8 @@ class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
}
|
||||
class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{5} = 1; // H bit
|
||||
let Inst{6} = 1; // S bit
|
||||
@ -465,8 +481,8 @@ class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
}
|
||||
class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{5} = 0; // H bit
|
||||
let Inst{6} = 1; // S bit
|
||||
@ -503,8 +519,8 @@ class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
}
|
||||
class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern> {
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
|
||||
asm, "", pattern> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{5} = 1; // H bit
|
||||
let Inst{6} = 0; // S bit
|
||||
|
||||
@ -472,31 +472,23 @@ def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
|
||||
|
||||
let AddedComplexity = 10 in {
|
||||
let isSimpleLoad = 1 in
|
||||
def PICLD : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
def PICLDR : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
|
||||
[(set GPR:$dst, (load addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDZH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
def PICLDRH : AXI3ldh<0xB, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
|
||||
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDZB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
def PICLDRB : AXI2ldb<0x1, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
|
||||
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
|
||||
[(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
|
||||
[(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDSH : AXI3ldsh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
def PICLDRSH : AXI3ldsh<0xE, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
|
||||
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
|
||||
|
||||
def PICLDSB : AXI3ldsb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
def PICLDRSB : AXI3ldsb<0xD, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
|
||||
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
|
||||
}
|
||||
@ -505,11 +497,11 @@ def PICSTR : AXI2stw<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
|
||||
[(store GPR:$src, addrmodepc:$addr)]>;
|
||||
|
||||
def PICSTRH : AXI3sth<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
||||
def PICSTRH : AXI3sth<0xB, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
|
||||
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
|
||||
|
||||
def PICSTRB : AXI2stb<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
||||
def PICSTRB : AXI2stb<0x1, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
||||
Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
|
||||
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
|
||||
}
|
||||
@ -1219,6 +1211,9 @@ def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
||||
def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
||||
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
|
||||
|
||||
def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
|
||||
def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
|
||||
|
||||
// smul* and smla*
|
||||
def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
|
||||
(SMULBB GPR:$a, GPR:$b)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user