mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
[mips] Fix FP branch instructions to have explicit FP condition code register
operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
ce0a12399c
commit
83d8ef133b
@ -123,6 +123,11 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
@ -158,12 +163,6 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBC1(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
|
||||
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
@ -407,6 +406,17 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
if (RegNo > 7)
|
||||
return MCDisassembler::Fail;
|
||||
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
|
||||
Inst.addOperand(MCOperand::CreateReg(Reg));
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMem(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
@ -529,16 +539,6 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBC1(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
unsigned BranchOffset = Insn & 0xffff;
|
||||
BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
|
||||
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
|
||||
@ -245,6 +245,14 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
|
||||
if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
|
||||
return true;
|
||||
break;
|
||||
case Mips::BC1T:
|
||||
if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS))
|
||||
return true;
|
||||
break;
|
||||
case Mips::BC1F:
|
||||
if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS))
|
||||
return true;
|
||||
break;
|
||||
case Mips::OR:
|
||||
if (isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS))
|
||||
return true;
|
||||
|
||||
@ -1438,8 +1438,9 @@ lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
|
||||
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
|
||||
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
|
||||
SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
|
||||
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
|
||||
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
|
||||
Dest, CondRes);
|
||||
FCC0, Dest, CondRes);
|
||||
}
|
||||
|
||||
SDValue MipsTargetLowering::
|
||||
|
||||
@ -24,8 +24,9 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Floating Point Compare and Branch
|
||||
def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
|
||||
SDTCisVT<1, OtherVT>]>;
|
||||
def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
|
||||
SDTCisVT<1, i32>,
|
||||
SDTCisVT<2, OtherVT>]>;
|
||||
def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
|
||||
SDTCisVT<2, i32>]>;
|
||||
def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
|
||||
@ -188,13 +189,13 @@ class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
|
||||
|
||||
class BC1F_FT<string opstr, InstrItinClass Itin,
|
||||
SDPatternOperator Op = null_frag> :
|
||||
InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
|
||||
[(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
|
||||
InstSE<(outs), (ins FCC:$fcc, brtarget:$offset),
|
||||
!strconcat(opstr, "\t$fcc, $offset"),
|
||||
[(MipsFPBrcond Op, FCC:$fcc, bb:$offset)], Itin, FrmFI> {
|
||||
let isBranch = 1;
|
||||
let isTerminator = 1;
|
||||
let hasDelaySlot = 1;
|
||||
let Defs = [AT];
|
||||
let Uses = [FCC0];
|
||||
}
|
||||
|
||||
class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
|
||||
@ -502,10 +503,9 @@ let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
|
||||
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
|
||||
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
|
||||
|
||||
let DecoderMethod = "DecodeBC1" in {
|
||||
def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
|
||||
def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Flag Conditions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -557,6 +557,12 @@ def ExtractElementF64 :
|
||||
[(set CPURegsOpnd:$dst,
|
||||
(MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// InstAliases.
|
||||
//===----------------------------------------------------------------------===//
|
||||
def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
|
||||
def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -665,13 +665,14 @@ class SWXC1_FM<bits<6> funct> {
|
||||
}
|
||||
|
||||
class BC1F_FM<bit nd, bit tf> {
|
||||
bits<3> fcc;
|
||||
bits<16> offset;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0x11;
|
||||
let Inst{25-21} = 0x8;
|
||||
let Inst{20-18} = 0; // cc
|
||||
let Inst{20-18} = fcc;
|
||||
let Inst{17} = nd;
|
||||
let Inst{16} = tf;
|
||||
let Inst{15-0} = offset;
|
||||
|
||||
@ -35,9 +35,15 @@
|
||||
# CHECK: bc1f 1332
|
||||
0x45 0x00 0x01 0x4c
|
||||
|
||||
# CHECK: bc1f $fcc7, 1332
|
||||
0x45 0x1c 0x01 0x4c
|
||||
|
||||
# CHECK: bc1t 1332
|
||||
0x45 0x01 0x01 0x4c
|
||||
|
||||
# CHECK: bc1t $fcc7, 1332
|
||||
0x45 0x1d 0x01 0x4c
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0x11 0x26 0x01 0x4c
|
||||
|
||||
|
||||
@ -35,9 +35,15 @@
|
||||
# CHECK: bc1f 1332
|
||||
0x4c 0x01 0x00 0x45
|
||||
|
||||
# CHECK: bc1f $fcc7, 1332
|
||||
0x4c 0x01 0x1c 0x45
|
||||
|
||||
# CHECK: bc1t 1332
|
||||
0x4c 0x01 0x01 0x45
|
||||
|
||||
# CHECK: bc1t $fcc7, 1332
|
||||
0x4c 0x01 0x1d 0x45
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0x4c 0x01 0x26 0x11
|
||||
|
||||
|
||||
@ -35,9 +35,15 @@
|
||||
# CHECK: bc1f 1332
|
||||
0x45 0x00 0x01 0x4c
|
||||
|
||||
# CHECK: bc1f $fcc7, 1332
|
||||
0x45 0x1c 0x01 0x4c
|
||||
|
||||
# CHECK: bc1t 1332
|
||||
0x45 0x01 0x01 0x4c
|
||||
|
||||
# CHECK: bc1t $fcc7, 1332
|
||||
0x45 0x1d 0x01 0x4c
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0x11 0x26 0x01 0x4c
|
||||
|
||||
|
||||
@ -35,9 +35,15 @@
|
||||
# CHECK: bc1f 1332
|
||||
0x4c 0x01 0x00 0x45
|
||||
|
||||
# CHECK: bc1f $fcc7, 1332
|
||||
0x4c 0x01 0x1c 0x45
|
||||
|
||||
# CHECK: bc1t 1332
|
||||
0x4c 0x01 0x01 0x45
|
||||
|
||||
# CHECK: bc1t $fcc7, 1332
|
||||
0x4c 0x01 0x1d 0x45
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0x4c 0x01 0x26 0x11
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user