mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-19 02:25:01 +00:00
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -493,7 +493,7 @@ EDInstInfo *MBlazeDisassembler::getEDInfo() const {
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// Public interface for the disassembler
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//
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bool MBlazeDisassembler::getInstruction(MCInst &instr,
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MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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@@ -508,7 +508,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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// We want to read exactly 4 bytes of data.
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if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read < 4)
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return false;
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return Fail;
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0);
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@@ -517,7 +517,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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// that it is a valid instruction.
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unsigned opcode = getOPCODE(insn);
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if (opcode == UNSUPPORTED)
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return false;
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return Fail;
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instr.setOpcode(opcode);
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@@ -529,11 +529,11 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
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switch ((tsFlags & MBlazeII::FormMask)) {
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default:
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return false;
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return Fail;
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case MBlazeII::FRRRR:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RB));
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instr.addOperand(MCOperand::CreateReg(RA));
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@@ -541,7 +541,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FRRR:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RA));
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instr.addOperand(MCOperand::CreateReg(RB));
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@@ -550,23 +550,23 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FRI:
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switch (opcode) {
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default:
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return false;
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return Fail;
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case MBlaze::MFS:
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if (RD == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
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break;
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case MBlaze::MTS:
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if (RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
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instr.addOperand(MCOperand::CreateReg(RA));
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break;
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case MBlaze::MSRSET:
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case MBlaze::MSRCLR:
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if (RD == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateImm(insn&0x7FFF));
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break;
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@@ -575,7 +575,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FRRI:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RA));
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switch (opcode) {
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@@ -592,35 +592,35 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FCRR:
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if (RA == UNSUPPORTED || RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RA));
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instr.addOperand(MCOperand::CreateReg(RB));
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break;
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case MBlazeII::FCRI:
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if (RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RA));
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instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
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break;
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case MBlazeII::FRCR:
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if (RD == UNSUPPORTED || RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RB));
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break;
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case MBlazeII::FRCI:
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if (RD == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
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break;
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case MBlazeII::FCCR:
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if (RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RB));
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break;
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@@ -630,7 +630,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FRRCI:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RA));
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instr.addOperand(MCOperand::CreateImm(getSHT(insn)));
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@@ -638,35 +638,35 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FRRC:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RA));
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break;
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case MBlazeII::FRCX:
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if (RD == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
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break;
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case MBlazeII::FRCS:
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if (RD == UNSUPPORTED || RS == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RS));
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break;
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case MBlazeII::FCRCS:
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if (RS == UNSUPPORTED || RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RS));
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instr.addOperand(MCOperand::CreateReg(RA));
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break;
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case MBlazeII::FCRCX:
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if (RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RA));
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instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
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break;
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@@ -677,13 +677,13 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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case MBlazeII::FCR:
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if (RB == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RB));
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break;
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case MBlazeII::FRIR:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED)
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return false;
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
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instr.addOperand(MCOperand::CreateReg(RA));
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@@ -693,7 +693,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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// We always consume 4 bytes of data on success
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size = 4;
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return true;
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return Success;
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}
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static MCDisassembler *createMBlazeDisassembler(const Target &T) {
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