mirror of
https://github.com/c64scene-ar/llvm-6502.git
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addrmode3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
0d14fc8cd5
commit
840917be2c
@ -155,7 +155,7 @@ class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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@ -163,7 +163,7 @@ class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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@ -173,7 +173,7 @@ class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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@ -181,19 +181,18 @@ class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: AI2<opcod, oops, iops, f, opc, asm, pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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}
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// Pre-indexed ops
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// loads
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// Pre-indexed loads
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class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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@ -202,18 +201,18 @@ class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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}
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// stores
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// Pre-indexed stores
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class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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@ -222,19 +221,18 @@ class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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}
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// Post-indexed ops
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// loads
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// Post-indexed loads
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class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 0; // P bit
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@ -243,18 +241,18 @@ class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{20} = 1; // load bit
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 0; // P bit
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}
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// stores
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// Post-indexed stores
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class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 0; // P bit
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@ -263,7 +261,7 @@ class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{20} = 0; // load bit
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 0; // P bit
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@ -275,6 +273,187 @@ class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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// loads
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class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 0; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 0; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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// stores
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class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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}
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// Pre-indexed loads
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class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 1; // P bit
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}
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class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 0; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 1; // P bit
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}
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// Pre-indexed stores
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class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 1; // P bit
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}
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// Post-indexed loads
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class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 0; // P bit
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}
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class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 0; // P bit
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}
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class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{4} = 1;
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let Inst{5} = 0; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 0; // P bit
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}
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// Post-indexed stores
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class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 0; // P bit
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}
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// addrmode4 instructions
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class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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@ -282,19 +461,6 @@ class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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asm, "", pattern>;
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// Pre-indexed ops
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class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern>;
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// Post-indexed ops
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class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern>;
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// Special cases.
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class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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@ -597,7 +597,7 @@ def LDRcp : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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"ldr", " $dst, $addr", []>;
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// Loads with zero extension
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def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRH : AI3ldh<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "h $dst, $addr",
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[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
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@ -606,17 +606,17 @@ def LDRB : AI2ldb<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
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// Loads with sign extension
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def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRSH : AI3ldsh<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "sh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
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def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRSB : AI3ldsb<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "sb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1 in {
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// Load doubleword
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def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRD : AI3ldd<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "d $dst, $addr",
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[]>, Requires<[IsARM, HasV5T]>;
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|
||||
@ -629,11 +629,11 @@ def LDR_POST : AI2ldwpo<0x0, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base, am2offset:$offset), LdFrm,
|
||||
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRH_PRE : AI3ldhpr<0xB, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdFrm,
|
||||
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRH_POST : AI3ldhpo<0xB, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdFrm,
|
||||
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
@ -645,19 +645,19 @@ def LDRB_POST : AI2ldbpo<0x1, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am2offset:$offset), LdFrm,
|
||||
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRSH_PRE : AI3ldshpr<0xE, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdFrm,
|
||||
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRSH_POST: AI3ldshpo<0xE, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdFrm,
|
||||
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRSB_PRE : AI3ldsbpr<0xD, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdFrm,
|
||||
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
|
||||
def LDRSB_POST: AI3ldsbpo<0xD, (outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdFrm,
|
||||
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
}
|
||||
@ -668,7 +668,7 @@ def STR : AI2stw<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
|
||||
[(store GPR:$src, addrmode2:$addr)]>;
|
||||
|
||||
// Stores with truncate
|
||||
def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
|
||||
def STRH : AI3sth<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
|
||||
"str", "h $src, $addr",
|
||||
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
|
||||
|
||||
@ -678,7 +678,7 @@ def STRB : AI2stb<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
|
||||
|
||||
// Store doubleword
|
||||
let mayStore = 1 in
|
||||
def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
|
||||
def STRD : AI3std<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
|
||||
"str", "d $src, $addr",
|
||||
[]>, Requires<[IsARM, HasV5T]>;
|
||||
|
||||
@ -695,13 +695,13 @@ def STR_POST : AI2stwpo<0x0, (outs GPR:$base_wb),
|
||||
[(set GPR:$base_wb,
|
||||
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
||||
|
||||
def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
|
||||
def STRH_PRE : AI3sthpr<0xB, (outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
|
||||
"str", "h $src, [$base, $offset]!", "$base = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
|
||||
|
||||
def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
|
||||
def STRH_POST: AI3sthpo<0xB, (outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
|
||||
"str", "h $src, [$base], $offset", "$base = $base_wb",
|
||||
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user