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[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-16 22:17:09 +00:00
parent 128b2c383c
commit 84201cb2bd
2 changed files with 19 additions and 47 deletions
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58
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -3048,53 +3048,25 @@ let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
(C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
// clrbit.
def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = clrbit($src1, #$src2)",
[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
(not
(shl 1, u5ImmPred:$src2))))]>;
def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = clrbit($src1, #$src2)",
[]>;
// Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
def : Pat <(and (i32 IntRegs:$src1), 2147483647),
(CLRBIT_31 (i32 IntRegs:$src1), 31)>;
// setbit.
def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = setbit($src1, #$src2)",
[(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
(shl 1, u5ImmPred:$src2)))]>;
// Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = setbit($src1, #$src2)",
[]>;
def : Pat <(or (i32 IntRegs:$src1), -2147483648),
(SETBIT_31 (i32 IntRegs:$src1), 31)>;
// togglebit.
def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = setbit($src1, #$src2)",
[(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
(shl 1, u5ImmPred:$src2)))]>;
// Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = togglebit($src1, #$src2)",
[]>;
def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
(TOGBIT_31 (i32 IntRegs:$src1), 31)>;
//===----------------------------------------------------------------------===//
// STYPE/BIT -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// STYPE/COMPLEX +
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// STYPE/COMPLEX -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// XTYPE/PERM +
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// XTYPE/PERM -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// STYPE/PRED +
//===----------------------------------------------------------------------===//

8
lib/Target/Hexagon/HexagonInstrInfoV5.td
View File

@ -587,19 +587,19 @@ def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
Requires<[HasV5T]>;
def : Pat <(fabs (f32 IntRegs:$src1)),
(CLRBIT_31 (f32 IntRegs:$src1), 31)>,
(S2_clrbit_i (f32 IntRegs:$src1), 31)>,
Requires<[HasV5T]>;
def : Pat <(fneg (f32 IntRegs:$src1)),
(TOGBIT_31 (f32 IntRegs:$src1), 31)>,
(S2_togglebit_i (f32 IntRegs:$src1), 31)>,
Requires<[HasV5T]>;
/*
def : Pat <(fabs (f64 DoubleRegs:$src1)),
(CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
(S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
Requires<[HasV5T]>;
def : Pat <(fabs (f64 DoubleRegs:$src1)),
(CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
(S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
Requires<[HasV5T]>;
*/