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The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8. rdar://problem/9247060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -536,7 +536,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
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return false;
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case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT:
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case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT:
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case ARM::SMMLA: case ARM::SMMLS:
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case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8:
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if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
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return true;
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return false;
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@ -545,6 +545,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
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case ARM::SMUAD: case ARM::SMUADX:
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// A8.6.167 SMLAD & A8.6.172 SMLSD
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case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX:
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case ARM::USAD8:
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if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15)
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return true;
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return false;
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@ -562,12 +563,13 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
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// Multiply Instructions.
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// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS,
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// SMLAD, SMLADX, SMLSD, SMLSDX:
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// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience):
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// Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
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// But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is
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// only for {d, n, m}.
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//
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// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX:
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// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX,
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// USAD8 (for convenience):
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// Rd{19-16} Rn{3-0} Rm{11-8}
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//
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// SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT,
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@ -77,3 +77,6 @@
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# CHECK: vmov r1, r0, d11
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0x1b 0x1b 0x50 0xec
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# CHECK: usada8mi r8, r9, r5, r9
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0x19 0x95 0x88 0x47
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