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DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7202,6 +7202,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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EVT ExtVT = VT.getVectorElementType();
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EVT LVT = ExtVT;
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// If the result of load has to be truncated, then it's not necessarily
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// profitable.
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if (NVT.bitsLT(LVT))
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return SDValue();
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if (InVec.getOpcode() == ISD::BITCAST) {
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// Don't duplicate a load with other uses.
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if (!InVec.hasOneUse())
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@ -7302,10 +7307,20 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// Note that this replacement assumes that the extractvalue is the only
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// use of the load; that's okay because we don't want to perform this
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// transformation in other cases anyway.
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SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
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LN0->getPointerInfo().getWithOffset(PtrOff),
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LN0->isVolatile(), LN0->isNonTemporal(),
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LN0->isInvariant(), Align);
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SDValue Load;
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if (NVT.bitsGT(LVT)) {
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// If the result type of vextract is wider than the load, then issue an
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// extending load instead.
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ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
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? ISD::ZEXTLOAD : ISD::EXTLOAD;
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Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
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NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
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LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
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} else
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Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
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LN0->getPointerInfo().getWithOffset(PtrOff),
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LN0->isVolatile(), LN0->isNonTemporal(),
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LN0->isInvariant(), Align);
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WorkListRemover DeadNodes(*this);
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SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
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SDValue To[] = { Load.getValue(0), Load.getValue(1) };
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16
test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
Normal file
16
test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
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; rdar://11035895
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; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
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; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e.
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; (i32 extload $addr+c*sizeof(i16)
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define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind {
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entry:
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; CHECK: ldrh [[REG:r[0-9]+]]
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; CHECK: strh [[REG]]
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%0 = load <3 x i16> * %srcA, align 8
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%1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>
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store <2 x i16> %1, <2 x i16> * %dst, align 4
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ret void
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}
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