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Just add a fixme about a possibly faster implementation of some atomic loads on some ARM processors

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218326 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robin Morisset 2014-09-23 18:33:21 +00:00
parent 226537a1d0
commit 8439e5e4c4
1 changed files with 3 additions and 0 deletions
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lib/Target/ARM/ARMISelLowering.cpp
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@ -11086,6 +11086,9 @@ bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
// are doomed anyway, so defer to the default libcall and blame the OS when
// things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
// anything for those.
// FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
// guarantee, see DDI0406C ARM architecture reference manual,
// sections A8.8.72-74 LDRD)
bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
unsigned Size = LI->getType()->getPrimitiveSizeInBits();
return (Size == 64) && !Subtarget->isMClass();