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Rewrite TargetMaterializeConstant.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113387 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-09-08 18:56:34 +00:00
parent 4a4bc3fba6
commit 845c5757ed
1 changed files with 18 additions and 7 deletions
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25
lib/Target/ARM/ARMFastISel.cpp
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@ -328,11 +328,12 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
// Only handle simple types.
if (!VT.isSimple()) return 0;
// Handle double width floating point?
if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
// TODO: This should be safe for fp because they're just bits from the
// Constant.
// TODO: Theoretically we could materialize fp constants with instructions
// from VFP3.
// TODO: Theoretically we could materialize fp constants directly with
// instructions from VFP3.
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(C->getType());
@ -342,8 +343,7 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
}
unsigned Idx = MCP.getConstantPoolIndex(C, Align);
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
// Different addressing modes between ARM/Thumb2 for constant pool loads.
unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::t2LDRpci))
@ -351,8 +351,19 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
else
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDRcp))
.addReg(DestReg).addConstantPoolIndex(Idx)
.addReg(DestReg).addConstantPoolIndex(Idx)
.addReg(0).addImm(0));
// If we have a floating point constant we expect it in a floating point
// register.
// TODO: Make this use ARMBaseInstrInfo::copyPhysReg.
if (C->getType()->isFloatTy()) {
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::VMOVRS), MoveReg)
.addReg(DestReg));
return MoveReg;
}
return DestReg;
}