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MC/ARM: Add an ARMOperand class for condition codes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-08-11 06:36:53 +00:00
parent ee34987fd5
commit 8462b30548
2 changed files with 30 additions and 4 deletions
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6
lib/Target/ARM/ARMInstrFormats.td
View File

@ -138,11 +138,17 @@ def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
// ARM special operands.
//
def CondCodeOperand : AsmOperandClass {
let Name = "CondCode";
let SuperClasses = [];
}
// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
// register whose default is 0 (no register).
def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
let ParserMatchClass = CondCodeOperand;
}
// Conditional code result for instructions whose 's' bit is set, e.g. subs.

28
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -106,15 +106,20 @@ private:
ARMOperand() {}
public:
enum KindTy {
Token,
Register,
CondCode,
Immediate,
Memory
Memory,
Register,
Token
} Kind;
SMLoc StartLoc, EndLoc;
union {
struct {
ARMCC::CondCodes Val;
} CC;
struct {
const char *Data;
unsigned Length;
@ -155,8 +160,11 @@ public:
StartLoc = o.StartLoc;
EndLoc = o.EndLoc;
switch (Kind) {
case CondCode:
CC = o.CC;
break;
case Token:
Tok = o.Tok;
Tok = o.Tok;
break;
case Register:
Reg = o.Reg;
@ -175,6 +183,11 @@ public:
/// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; }
ARMCC::CondCodes getCondCode() const {
assert(Kind == CondCode && "Invalid access!");
return CC.Val;
}
StringRef getToken() const {
assert(Kind == Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length);
@ -190,6 +203,8 @@ public:
return Imm.Val;
}
bool isCondCode() const { return Kind == CondCode; }
bool isImm() const { return Kind == Immediate; }
bool isReg() const { return Kind == Register; }
@ -204,6 +219,11 @@ public:
Inst.addOperand(MCOperand::CreateExpr(Expr));
}
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getReg()));