6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-14 16:33:28 +00:00
Code Issues Projects Releases Wiki Activity

Move getAnalysisUsage method from header to .cpp file. Add a normal file

Browse Source 
header comment


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-09-23 15:13:04 +00:00
parent 5c344415fa
commit 8474f6fcda
4 changed files with 44 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -43,6 +43,12 @@ FunctionPass *getRegisterAllocator(TargetMachine &T) {
return new PhyRegAlloc (T);
}
void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LoopInfo> ();
AU.addRequired<FunctionLiveVarInfo> ();
}
//----------------------------------------------------------------------------
// This method initially creates interference graphs (one in each reg class)

37
lib/CodeGen/RegAlloc/PhyRegAlloc.h
View File

@ -1,20 +1,18 @@
/* Title: PhyRegAlloc.h -*- C++ -*-
Author: Ruchira Sasanka
Date: Aug 20, 01
Purpose: This is the main entry point for register allocation.
Notes:
=====
* RegisterClasses: Each RegClass accepts a
TargetRegClass which contains machine specific info about that register
class. The code in the RegClass is machine independent and they use
access functions in the TargetRegClass object passed into it to get
machine specific info.
* Machine dependent work: All parts of the register coloring algorithm
except coloring of an individual node are machine independent.
*/
//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
//
// This is the main entry point for register allocation.
//
// Notes:
// * RegisterClasses: Each RegClass accepts a
// TargetRegClass which contains machine specific info about that register
// class. The code in the RegClass is machine independent and they use
// access functions in the TargetRegClass object passed into it to get
// machine specific info.
//
// * Machine dependent work: All parts of the register coloring algorithm
// except coloring of an individual node are machine independent.
//
//===----------------------------------------------------------------------===//
#ifndef PHYREGALLOC_H
#define PHYREGALLOC_H
@ -91,10 +89,7 @@ public:
///
virtual bool runOnFunction (Function &F);
virtual void getAnalysisUsage (AnalysisUsage &AU) const {
AU.addRequired<LoopInfo> ();
AU.addRequired<FunctionLiveVarInfo> ();
}
virtual void getAnalysisUsage (AnalysisUsage &AU) const;
const char *getPassName () const {
return "Traditional graph-coloring reg. allocator";

6
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -43,6 +43,12 @@ FunctionPass *getRegisterAllocator(TargetMachine &T) {
return new PhyRegAlloc (T);
}
void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LoopInfo> ();
AU.addRequired<FunctionLiveVarInfo> ();
}
//----------------------------------------------------------------------------
// This method initially creates interference graphs (one in each reg class)

37
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
View File

@ -1,20 +1,18 @@
/* Title: PhyRegAlloc.h -*- C++ -*-
Author: Ruchira Sasanka
Date: Aug 20, 01
Purpose: This is the main entry point for register allocation.
Notes:
=====
* RegisterClasses: Each RegClass accepts a
TargetRegClass which contains machine specific info about that register
class. The code in the RegClass is machine independent and they use
access functions in the TargetRegClass object passed into it to get
machine specific info.
* Machine dependent work: All parts of the register coloring algorithm
except coloring of an individual node are machine independent.
*/
//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
//
// This is the main entry point for register allocation.
//
// Notes:
// * RegisterClasses: Each RegClass accepts a
// TargetRegClass which contains machine specific info about that register
// class. The code in the RegClass is machine independent and they use
// access functions in the TargetRegClass object passed into it to get
// machine specific info.
//
// * Machine dependent work: All parts of the register coloring algorithm
// except coloring of an individual node are machine independent.
//
//===----------------------------------------------------------------------===//
#ifndef PHYREGALLOC_H
#define PHYREGALLOC_H
@ -91,10 +89,7 @@ public:
///
virtual bool runOnFunction (Function &F);
virtual void getAnalysisUsage (AnalysisUsage &AU) const {
AU.addRequired<LoopInfo> ();
AU.addRequired<FunctionLiveVarInfo> ();
}
virtual void getAnalysisUsage (AnalysisUsage &AU) const;
const char *getPassName () const {
return "Traditional graph-coloring reg. allocator";