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1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
(~x)|y and x|(~y) yielding ORC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22771 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1717,10 +1717,17 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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}
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}
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if (isOprNot(N.getOperand(1))) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
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RecordSuccess = false;
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return Result;
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}
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if (isOprNot(N.getOperand(0))) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1);
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
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RecordSuccess = false;
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return Result;
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}
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@ -1737,6 +1744,20 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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if (SelectIntImmediateExpr(N, Result, PPC::ORIS, PPC::ORI))
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return Result;
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if (isOprNot(N.getOperand(1))) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
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RecordSuccess = false;
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return Result;
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}
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if (isOprNot(N.getOperand(0))) {
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
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RecordSuccess = false;
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return Result;
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}
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// emit regular or
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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