6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-12 13:30:51 +00:00
Code Issues Projects Releases Wiki Activity

Cache and use the subtarget that owns the target lowering.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-02-02 22:11:36 +00:00
parent d821e0a5cc
commit 848278638c
3 changed files with 20 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -463,8 +463,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
SmallVector<SDValue, 8> MemOpChains; SmallVector<SDValue, 8> MemOpChains;
const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
DAG.getSubtarget().getRegisterInfo());
SDValue StackPtr = SDValue StackPtr =
DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy()); DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy());
@ -722,9 +721,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
cast<RegisterSDNode>(Node->getOperand(i))->getReg(); cast<RegisterSDNode>(Node->getOperand(i))->getReg();
// Check it to be lr // Check it to be lr
const HexagonRegisterInfo *QRI = const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
static_cast<const HexagonRegisterInfo *>(
DAG.getSubtarget().getRegisterInfo());
if (Reg == QRI->getRARegister()) { if (Reg == QRI->getRARegister()) {
FuncInfo->setHasClobberLR(true); FuncInfo->setHasClobberLR(true);
break; break;
@ -817,8 +814,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
// The Sub result contains the new stack start address, so it // The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register. // must be placed in the stack pointer register.
const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
DAG.getSubtarget().getRegisterInfo());
SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub); SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub);
SDValue Ops[2] = { ArgAdjust, CopyChain }; SDValue Ops[2] = { ArgAdjust, CopyChain };
@ -965,7 +961,7 @@ HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
SDValue SDValue
HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MFI->setReturnAddressIsTaken(true); MFI->setReturnAddressIsTaken(true);
@ -991,8 +987,7 @@ HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
SDValue SDValue
HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
const HexagonRegisterInfo *TRI = static_cast<const HexagonRegisterInfo *>( const HexagonRegisterInfo *TRI = Subtarget->getRegisterInfo();
DAG.getSubtarget().getRegisterInfo());
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true); MFI->setFrameAddressIsTaken(true);
@ -1044,17 +1039,15 @@ HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
// TargetLowering Implementation // TargetLowering Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
: TargetLowering(targetmachine), const HexagonSubtarget &STI)
TM(targetmachine) { : TargetLowering(TM), Subtarget(&STI) {
const HexagonSubtarget &Subtarget = TM.getSubtarget<HexagonSubtarget>();
// Set up the register classes. // Set up the register classes.
addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
if (Subtarget.hasV5TOps()) { if (Subtarget->hasV5TOps()) {
addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
} }
@ -1120,7 +1113,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setOperationAction(ISD::FSIN, MVT::f32, Expand); setOperationAction(ISD::FSIN, MVT::f32, Expand);
setOperationAction(ISD::FSIN, MVT::f64, Expand); setOperationAction(ISD::FSIN, MVT::f64, Expand);
if (Subtarget.hasV5TOps()) { if (Subtarget->hasV5TOps()) {
// Hexagon V5 Support. // Hexagon V5 Support.
setOperationAction(ISD::FADD, MVT::f32, Legal); setOperationAction(ISD::FADD, MVT::f32, Legal);
setOperationAction(ISD::FADD, MVT::f64, Expand); setOperationAction(ISD::FADD, MVT::f64, Expand);
@ -1346,7 +1339,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
if (Subtarget.hasV5TOps()) { if (Subtarget->hasV5TOps()) {
// We need to make the operation type of SELECT node to be Custom, // We need to make the operation type of SELECT node to be Custom,
// such that we don't go into the infinite loop of // such that we don't go into the infinite loop of
@ -1441,7 +1434,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
if (Subtarget.isSubtargetV2()) { if (Subtarget->isSubtargetV2()) {
setExceptionPointerRegister(Hexagon::R20); setExceptionPointerRegister(Hexagon::R20);
setExceptionSelectorRegister(Hexagon::R21); setExceptionSelectorRegister(Hexagon::R21);
} else { } else {
@ -1465,8 +1458,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setMinFunctionAlignment(2); setMinFunctionAlignment(2);
// Needed for DYNAMIC_STACKALLOC expansion. // Needed for DYNAMIC_STACKALLOC expansion.
const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
TM.getSubtargetImpl()->getRegisterInfo());
setStackPointerRegisterToSaveRestore(QRI->getStackRegister()); setStackPointerRegisterToSaveRestore(QRI->getStackRegister());
setSchedulingPreference(Sched::VLIW); setSchedulingPreference(Sched::VLIW);
} }
@ -1637,7 +1629,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
/// specified FP immediate natively. If false, the legalizer will /// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool. /// materialize the FP immediate as a load from a constant pool.
bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
return TM.getSubtarget<HexagonSubtarget>().hasV5TOps(); return Subtarget->hasV5TOps();
} }
/// isLegalAddressingMode - Return true if the addressing mode represented by /// isLegalAddressingMode - Return true if the addressing mode represented by

7
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -77,6 +77,8 @@ bool isPositiveHalfWord(SDNode *N);
}; };
} }
class HexagonSubtarget;
class HexagonTargetLowering : public TargetLowering { class HexagonTargetLowering : public TargetLowering {
int VarArgsFrameOffset; // Frame offset to start of varargs area. int VarArgsFrameOffset; // Frame offset to start of varargs area.
@ -84,8 +86,9 @@ bool isPositiveHalfWord(SDNode *N);
unsigned& RetSize) const; unsigned& RetSize) const;
public: public:
const TargetMachine &TM; const HexagonSubtarget *Subtarget;
explicit HexagonTargetLowering(const TargetMachine &targetmachine); explicit HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &Subtarget);
/// IsEligibleForTailCallOptimization - Check whether the call is eligible /// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Targets which want to do tail call /// for tail call optimization. Targets which want to do tail call

2
lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -74,7 +74,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
const TargetMachine &TM) const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()), : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()), FrameLowering() { TSInfo(*TM.getDataLayout()), FrameLowering() {
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.