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https://github.com/c64scene-ar/llvm-6502.git
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simplify displacement handling, emit displacements by-operand
even for the immediate case. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95770 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -68,8 +68,8 @@ public:
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}
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}
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void EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const;
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void EmitDisplacementField(const MCOperand &Disp, int64_t Adj, bool IsPCRel,
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raw_ostream &OS) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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@ -119,12 +119,12 @@ static bool isDisp8(int Value) {
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}
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void X86MCCodeEmitter::
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EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const {
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EmitDisplacementField(const MCOperand &DispOp, int64_t Adj, bool IsPCRel,
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raw_ostream &OS) const {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (!RelocOp) {
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EmitConstant(DispVal, 4, OS);
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if (DispOp.isImm()) {
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EmitConstant(DispOp.getImm(), 4, OS);
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return;
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}
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@ -159,39 +159,8 @@ EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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intptr_t PCAdj,
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raw_ostream &OS) const {
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const MCOperand &Op3 = MI.getOperand(Op+3);
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int DispVal = 0;
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const MCOperand *DispForReloc = 0;
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// Figure out what sort of displacement we have to handle here.
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if (Op3.isImm()) {
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DispVal = Op3.getImm();
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} else {
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assert(0 && "relocatable operand");
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#if 0
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if (Op3.isGlobal()) {
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DispForReloc = &Op3;
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} else if (Op3.isSymbol()) {
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DispForReloc = &Op3;
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} else if (Op3.isCPI()) {
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
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DispVal += Op3.getOffset();
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}
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} else {
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assert(Op3.isJTI());
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
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}
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#endif
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}
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intptr_t PCAdj, raw_ostream &OS) const {
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const MCOperand &Disp = MI.getOperand(Op+3);
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const MCOperand &Base = MI.getOperand(Op);
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const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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@ -215,7 +184,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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if (BaseReg == 0 || // [disp32] in X86-32 mode
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BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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EmitByte(ModRMByte(0, RegOpcodeField, 5), OS);
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, true, OS);
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EmitDisplacementField(Disp, PCAdj, true, OS);
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return;
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}
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@ -225,21 +194,21 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// indirect register encoding, this handles addresses like [EAX]. The
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// encoding for [EBP] with no displacement means [disp32] so we handle it
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// by emitting a displacement of 0 below.
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
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EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), OS);
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return;
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}
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// Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
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if (!DispForReloc && isDisp8(DispVal)) {
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if (Disp.isImm() && isDisp8(Disp.getImm())) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), OS);
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EmitConstant(DispVal, 1, OS);
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EmitConstant(Disp.getImm(), 1, OS);
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return;
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}
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// Otherwise, emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), OS);
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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EmitDisplacementField(Disp, PCAdj, IsPCRel, OS);
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return;
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}
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@ -254,14 +223,14 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispForReloc) {
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} else if (!Disp.isImm()) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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} else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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} else if (isDisp8(DispVal)) {
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} else if (isDisp8(Disp.getImm())) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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@ -294,9 +263,9 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// Do we need to output a displacement?
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if (ForceDisp8)
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EmitConstant(DispVal, 1, OS);
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else if (DispVal != 0 || ForceDisp32)
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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EmitConstant(Disp.getImm(), 1, OS);
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else if (ForceDisp32 || Disp.getImm() != 0)
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EmitDisplacementField(Disp, PCAdj, IsPCRel, OS);
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}
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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