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Fix expansion of vsetcc to set the high bit for true instead of 1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61129 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2008-12-17 08:49:47 +00:00
parent f49a28cd02
commit 84aff84cfa
1 changed files with 6 additions and 4 deletions
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10
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3144,10 +3144,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
Tmp1, DAG.getIntPtrConstant(i));
Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
Tmp2, DAG.getIntPtrConstant(i)),
CC);
Ops[i] = DAG.getNode(ISD::SIGN_EXTEND, EltVT, Ops[i]);
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
Tmp2, DAG.getIntPtrConstant(i)),
CC);
Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
DAG.getConstant(0, EltVT));
}
Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
break;