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Fix expansion of vsetcc to set the high bit for true instead of 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61129 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3144,10 +3144,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
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Tmp1, DAG.getIntPtrConstant(i));
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Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
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Tmp2, DAG.getIntPtrConstant(i)),
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CC);
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Ops[i] = DAG.getNode(ISD::SIGN_EXTEND, EltVT, Ops[i]);
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
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Tmp2, DAG.getIntPtrConstant(i)),
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CC);
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Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
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DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
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DAG.getConstant(0, EltVT));
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}
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Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
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break;
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