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Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24783 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -107,25 +107,29 @@ let rd = 0 in
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"cmp $b, $c", []>;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsb [$b+$c], $dst", []>;
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def LDSH: F3_2<3, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsh [$b+$c], $dst", []>;
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def LDUB: F3_2<3, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldub [$b+$c], $dst", []>;
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def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"lduh [$b+$c], $dst", []>;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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def LDSBri : F3_2<3, 0b001001,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldsb [$addr], $dst",
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[(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
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def LDSHri : F3_2<3, 0b001010,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldsh [$addr], $dst",
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[(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
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def LDUBri : F3_2<3, 0b000001,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldub [$addr], $dst",
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[(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
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def LDUHri : F3_2<3, 0b000010,
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(ops IntRegs:$dst, MEMri:$addr),
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"lduh [$addr], $dst",
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[(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
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def LDri : F3_2<3, 0b000000,
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDDri : F3_2<3, 0b000011,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldd [$addr], $dst", []>;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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@ -148,18 +152,18 @@ def LDFSRri: F3_2<3, 0b100001,
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"ld [$b+$c], $dst", []>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STB : F3_2<3, 0b000101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"stb $src, [$base+$offset]", []>;
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def STH : F3_2<3, 0b000110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"sth $src, [$base+$offset]", []>;
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def ST : F3_2<3, 0b000100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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def STD : F3_2<3, 0b000111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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def STBri : F3_2<3, 0b000101,
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(ops MEMri:$addr, IntRegs:$src),
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"stb $src, [$addr]", []>;
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def STHri : F3_2<3, 0b000110,
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(ops MEMri:$addr, IntRegs:$src),
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"sth $src, [$addr]", []>;
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def STri : F3_2<3, 0b000100,
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDri : F3_2<3, 0b000111,
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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@ -107,25 +107,29 @@ let rd = 0 in
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"cmp $b, $c", []>;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsb [$b+$c], $dst", []>;
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def LDSH: F3_2<3, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsh [$b+$c], $dst", []>;
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def LDUB: F3_2<3, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldub [$b+$c], $dst", []>;
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def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"lduh [$b+$c], $dst", []>;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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def LDSBri : F3_2<3, 0b001001,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldsb [$addr], $dst",
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[(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
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def LDSHri : F3_2<3, 0b001010,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldsh [$addr], $dst",
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[(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
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def LDUBri : F3_2<3, 0b000001,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldub [$addr], $dst",
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[(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
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def LDUHri : F3_2<3, 0b000010,
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(ops IntRegs:$dst, MEMri:$addr),
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"lduh [$addr], $dst",
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[(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
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def LDri : F3_2<3, 0b000000,
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDDri : F3_2<3, 0b000011,
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(ops IntRegs:$dst, MEMri:$addr),
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"ldd [$addr], $dst", []>;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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@ -148,18 +152,18 @@ def LDFSRri: F3_2<3, 0b100001,
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"ld [$b+$c], $dst", []>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STB : F3_2<3, 0b000101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"stb $src, [$base+$offset]", []>;
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def STH : F3_2<3, 0b000110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"sth $src, [$base+$offset]", []>;
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def ST : F3_2<3, 0b000100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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def STD : F3_2<3, 0b000111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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def STBri : F3_2<3, 0b000101,
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(ops MEMri:$addr, IntRegs:$src),
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"stb $src, [$addr]", []>;
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def STHri : F3_2<3, 0b000110,
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(ops MEMri:$addr, IntRegs:$src),
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"sth $src, [$addr]", []>;
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def STri : F3_2<3, 0b000100,
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDri : F3_2<3, 0b000111,
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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