mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi
My original LE implementation of the vsldoi instruction, with its altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect shufflevector operations in the LLVM IR. Correct code is generated because the back end handles the incorrect shufflevector in a consistent manner. This patch and a companion patch for Clang correct this problem by removing the fixup from altivec.h and the corresponding fixup from the PowerPC back end. Several test cases are also modified to reflect the now-correct LLVM IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214800 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2a78a0cd47
commit
84fef1f55d
@ -1009,24 +1009,6 @@ int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
|
||||
unsigned ShiftAmt = SVOp->getMaskElt(i);
|
||||
if (ShiftAmt < i) return -1;
|
||||
|
||||
if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
|
||||
|
||||
ShiftAmt += i;
|
||||
|
||||
if (!isUnary) {
|
||||
// Check the rest of the elements to see if they are consecutive.
|
||||
for (++i; i != 16; ++i)
|
||||
if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
|
||||
return -1;
|
||||
} else {
|
||||
// Check the rest of the elements to see if they are consecutive.
|
||||
for (++i; i != 16; ++i)
|
||||
if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
|
||||
return -1;
|
||||
}
|
||||
|
||||
} else { // Big Endian
|
||||
|
||||
ShiftAmt -= i;
|
||||
|
||||
if (!isUnary) {
|
||||
@ -1040,7 +1022,7 @@ int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
|
||||
if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return ShiftAmt;
|
||||
}
|
||||
|
||||
|
@ -189,7 +189,7 @@ entry:
|
||||
; CHECK: VSLDOI_xy:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
|
||||
; CHECK: vsldoi
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
@ -199,7 +199,7 @@ define void @VSLDOI_xx(<16 x i8>* %A) {
|
||||
entry:
|
||||
; CHECK: VSLDOI_xx:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
|
||||
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK: vsldoi
|
||||
store <16 x i8> %tmp2, <16 x i8>* %A
|
||||
ret void
|
||||
|
Loading…
Reference in New Issue
Block a user