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Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit

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expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2010-03-10 18:12:27 +00:00
parent 0965200ac2
commit 850f1cd3c0
2 changed files with 44 additions and 2 deletions
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test/CodeGen/XCore/addsub64.ll
+15
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@@ -42,3 +42,18 @@ entry:
; CHECK: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0
define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
%0 = zext i32 %a to i64
%1 = zext i32 %b to i64
%2 = zext i32 %c to i64
%3 = zext i32 %d to i64
%4 = mul i64 %1, %0
%5 = add i64 %4, %2
%6 = add i64 %5, %3
ret i64 %6
}
; CHECK: lmul:
; CHECK: lmul r1, r0, r1, r0, r2, r3
; CHECK-NEXT: retsp 0